From b5e7690f11aa478711ea53d0dfe3047b9d03e9b7 Mon Sep 17 00:00:00 2001
From: uuuvn <uuuvn@uuuvn.space>
Date: Sat, 10 Jun 2023 11:53:20 +0000
Subject: [PATCH] Fix misconfigured MAIR_L1 register so kernel doesn't explode
early on boot
---
src/os/uefi/arch/aarch64.rs | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/os/uefi/arch/aarch64.rs b/src/os/uefi/arch/aarch64.rs
index 361122b..182eff2 100644
--- a/src/os/uefi/arch/aarch64.rs
+++ b/src/os/uefi/arch/aarch64.rs
@@ -58,9 +58,17 @@ unsafe extern "C" fn kernel_entry(
);
// Set MAIR
+ // You can think about MAIRs as of an array with 8 elements each of 8 bits long.
+ // You can store inside MAIRs up to 8 attributes sets and reffer them by the index 0..7 stored in INDX (AttrIndx) field of the table descriptor.
+ // https://lowenware.com/blog/aarch64-mmu-programming/
+ // https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64
+ // https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/MAIR-EL1--Memory-Attribute-Indirection-Register--EL1-
+ // Attribute 0 (0xFF) - normal memory, caches are enabled
+ // Attribute 1 (0x44) - normal memory, caches are disabled. Atomics wouldn't work here if memory doesn't support exclusive access (most real hardware don't)
+ // Attribute 2 (0x00) - nGnRnE device memory, caches are disabled, gathering, re-ordering, and early write acknowledgement aren't allowed.
asm!(
"msr mair_el1, {0}",
- in(reg) 0xff4400, // MAIR: Arrange for Device, Normal Non-Cache, Normal Write-Back access types
+ in(reg) 0x00000000000044FF as u64, // MAIR: Arrange for Device, Normal Non-Cache, Normal Write-Back access types
);
// Set TCR
--
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