Commit 329750af authored by Jeremy Soller's avatar Jeremy Soller

Remove debug prints

parent 5bccc801
...@@ -140,7 +140,6 @@ impl HbaPort { ...@@ -140,7 +140,6 @@ impl HbaPort {
// Shared between identify() and identify_packet() // Shared between identify() and identify_packet()
unsafe fn identify_inner(&mut self, cmd: u8, clb: &mut Dma<[HbaCmdHeader; 32]>, ctbas: &mut [Dma<HbaCmdTable>; 32]) -> Option<u64> { unsafe fn identify_inner(&mut self, cmd: u8, clb: &mut Dma<[HbaCmdHeader; 32]>, ctbas: &mut [Dma<HbaCmdTable>; 32]) -> Option<u64> {
let dest: Dma<[u16; 256]> = Dma::new([0; 256]).unwrap(); let dest: Dma<[u16; 256]> = Dma::new([0; 256]).unwrap();
let res = self.ata_dma(clb, ctbas, |cmdheader, cmdfis, prdt_entries, _acmd| { let res = self.ata_dma(clb, ctbas, |cmdheader, cmdfis, prdt_entries, _acmd| {
......
...@@ -113,8 +113,6 @@ impl SchemeMut for Rtl8168 { ...@@ -113,8 +113,6 @@ impl SchemeMut for Rtl8168 {
let eor = rd.ctrl.read() & EOR; let eor = rd.ctrl.read() & EOR;
rd.ctrl.write(OWN | eor | data.len() as u32); rd.ctrl.write(OWN | eor | data.len() as u32);
print!("{}", format!("rtl8168d: read {}: {}\n", self.receive_i, i));
self.receive_i += 1; self.receive_i += 1;
return Ok(i); return Ok(i);
...@@ -152,8 +150,6 @@ impl SchemeMut for Rtl8168 { ...@@ -152,8 +150,6 @@ impl SchemeMut for Rtl8168 {
thread::yield_now(); thread::yield_now();
} }
print!("{}", format!("rtl8168d: write {}: {}\n", self.transmit_i, i));
self.transmit_i += 1; self.transmit_i += 1;
return Ok(i); return Ok(i);
......
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