diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 82646875ace67816517c876d699c957c085b0b42..4ef531ab020f3027ecf50e6507fff4300ccd2281 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,24 @@
+2007-01-19 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (acos<mode>2): Rename from acossf2 and acosdf2.
+ Macroize expander using X87MODEF12 mode macro. Extend operand 1
+ to XFMode, use acosxf2 and truncate result to requested mode.
+ Use SSE_FLOAT_MODE_P to disable patterns for SSE math.
+ (asin<mode>2): Similarly, with asin expanders.
+ (*fscalexf4_i387): Rename from *fscalexf4.
+ (expNcorexf3): New expander.
+ (expxf2, exp10xf2, exp2xf2): Use expNcorexf3 expander.
+ (exp<mode>2): Rename from expsf2 and expdf2. Macroize expander using
+ X87MODEF12 mode macro. Extend operand 1 to XFMode, use expxf2 and
+ truncate result to requested mode. Use SSE_FLOAT_MODE_P to disable
+ patterns for SSE math.
+ (exp10<mode>2): Similarly, with exp10 expanders.
+ (exp2<mode>2): Similarly, with exp2 expanders.
+ (expm1<mode>2): Similarly, with expm1 expanders.
+ (ldexp<mode>3): Similarly, with ldexp expanders.
+ (log<mode>2, log10<mode>2, log2<mode>2, log1p<mode>2, logb<mode>2):
+ Use gen_truncxf<mode>2_i387_noop to truncate result.
+
2007-01-19 Richard Sandiford <richard@codesourcery.com>
* config/m68k/m68k.h (PREFERRED_STACK_BOUNDARY): Define to 32
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 9766548ef0a989376de20ded28fa0ca1368b695c..fb3a41bbe4f1a9d528589f0835f890caaabbfd6c 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -16012,54 +16012,6 @@
DONE;
})
-(define_expand "asindf2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:DF 1 "register_operand" "")))
- (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
- (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
- (set (match_dup 6) (sqrt:XF (match_dup 5)))
- (parallel [(set (match_dup 7)
- (unspec:XF [(match_dup 6) (match_dup 2)]
- UNSPEC_FPATAN))
- (clobber (match_scratch:XF 8 ""))])
- (set (match_operand:DF 0 "register_operand" "")
- (float_truncate:DF (match_dup 7)))]
- "TARGET_USE_FANCY_MATH_387
- && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
-{
- int i;
-
- for (i=2; i<8; i++)
- operands[i] = gen_reg_rtx (XFmode);
-
- emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
-})
-
-(define_expand "asinsf2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:SF 1 "register_operand" "")))
- (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
- (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
- (set (match_dup 6) (sqrt:XF (match_dup 5)))
- (parallel [(set (match_dup 7)
- (unspec:XF [(match_dup 6) (match_dup 2)]
- UNSPEC_FPATAN))
- (clobber (match_scratch:XF 8 ""))])
- (set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF (match_dup 7)))]
- "TARGET_USE_FANCY_MATH_387
- && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
-{
- int i;
-
- for (i=2; i<8; i++)
- operands[i] = gen_reg_rtx (XFmode);
-
- emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
-})
-
(define_expand "asinxf2"
[(set (match_dup 2)
(mult:XF (match_operand:XF 1 "register_operand" "")
@@ -16075,58 +16027,27 @@
{
int i;
- for (i=2; i<6; i++)
+ for (i = 2; i < 6; i++)
operands[i] = gen_reg_rtx (XFmode);
emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
})
-(define_expand "acosdf2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:DF 1 "register_operand" "")))
- (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
- (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
- (set (match_dup 6) (sqrt:XF (match_dup 5)))
- (parallel [(set (match_dup 7)
- (unspec:XF [(match_dup 2) (match_dup 6)]
- UNSPEC_FPATAN))
- (clobber (match_scratch:XF 8 ""))])
- (set (match_operand:DF 0 "register_operand" "")
- (float_truncate:DF (match_dup 7)))]
- "TARGET_USE_FANCY_MATH_387
- && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
-{
- int i;
-
- for (i=2; i<8; i++)
- operands[i] = gen_reg_rtx (XFmode);
-
- emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
-})
-
-(define_expand "acossf2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:SF 1 "register_operand" "")))
- (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
- (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
- (set (match_dup 6) (sqrt:XF (match_dup 5)))
- (parallel [(set (match_dup 7)
- (unspec:XF [(match_dup 2) (match_dup 6)]
- UNSPEC_FPATAN))
- (clobber (match_scratch:XF 8 ""))])
- (set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF (match_dup 7)))]
- "TARGET_USE_FANCY_MATH_387
- && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
+(define_expand "asin<mode>2"
+ [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+ (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations && !optimize_size"
{
- int i;
-
- for (i=2; i<8; i++)
- operands[i] = gen_reg_rtx (XFmode);
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
- emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_asinxf2 (op0, op1));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
+ DONE;
})
(define_expand "acosxf2"
@@ -16144,12 +16065,29 @@
{
int i;
- for (i=2; i<6; i++)
+ for (i = 2; i < 6; i++)
operands[i] = gen_reg_rtx (XFmode);
emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
})
+(define_expand "acos<mode>2"
+ [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+ (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
+ && flag_unsafe_math_optimizations && !optimize_size"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_acosxf2 (op0, op1));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
+ DONE;
+})
+
(define_insn "fyl2xxf3_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")
@@ -16203,7 +16141,7 @@
emit_move_insn (operands[2], standard_80387_constant_rtx (4)); /* fldln2 */
emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], operands[2]));
- emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
DONE;
})
@@ -16233,7 +16171,7 @@
emit_move_insn (operands[2], standard_80387_constant_rtx (3)); /* fldlg2 */
emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], operands[2]));
- emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
DONE;
})
@@ -16263,7 +16201,7 @@
emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], operands[2]));
- emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
DONE;
})
@@ -16317,7 +16255,7 @@
operands[1] = gen_rtx_FLOAT_EXTEND (XFmode, operands[1]);
ix86_emit_i387_log1p (op0, operands[1]);
- emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
DONE;
})
@@ -16372,7 +16310,7 @@
rtx op1 = gen_reg_rtx (XFmode);
emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
- emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op1));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op1));
DONE;
})
@@ -16393,17 +16331,17 @@
operands[3] = gen_reg_rtx (XFmode);
})
-(define_insn "*f2xm1xf2"
+(define_insn "*f2xm1xf2_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
- UNSPEC_F2XM1))]
+ UNSPEC_F2XM1))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"f2xm1"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
-(define_insn "*fscalexf4"
+(define_insn "*fscalexf4_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 2 "register_operand" "0")
(match_operand:XF 3 "register_operand" "1")]
@@ -16417,69 +16355,9 @@
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
-(define_expand "expsf2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:SF 1 "register_operand" "")))
- (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
- (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
- (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
- (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
- (parallel [(set (match_dup 10)
- (unspec:XF [(match_dup 9) (match_dup 5)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 11)
- (unspec:XF [(match_dup 9) (match_dup 5)]
- UNSPEC_FSCALE_EXP))])
- (set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF (match_dup 10)))]
- "TARGET_USE_FANCY_MATH_387
- && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
-{
- rtx temp;
- int i;
-
- for (i=2; i<12; i++)
- operands[i] = gen_reg_rtx (XFmode);
- temp = standard_80387_constant_rtx (5); /* fldl2e */
- emit_move_insn (operands[3], temp);
- emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
-})
-
-(define_expand "expdf2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:DF 1 "register_operand" "")))
- (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
- (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
- (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
- (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
- (parallel [(set (match_dup 10)
- (unspec:XF [(match_dup 9) (match_dup 5)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 11)
- (unspec:XF [(match_dup 9) (match_dup 5)]
- UNSPEC_FSCALE_EXP))])
- (set (match_operand:DF 0 "register_operand" "")
- (float_truncate:DF (match_dup 10)))]
- "TARGET_USE_FANCY_MATH_387
- && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
-{
- rtx temp;
- int i;
-
- for (i=2; i<12; i++)
- operands[i] = gen_reg_rtx (XFmode);
- temp = standard_80387_constant_rtx (5); /* fldl2e */
- emit_move_insn (operands[3], temp);
- emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
-})
-
-(define_expand "expxf2"
+(define_expand "expNcorexf3"
[(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
- (match_dup 2)))
+ (match_operand:XF 2 "register_operand" "")))
(set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
(set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
(set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
@@ -16493,248 +16371,102 @@
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations && !optimize_size"
{
- rtx temp;
int i;
- for (i=2; i<10; i++)
+ for (i = 3; i < 10; i++)
operands[i] = gen_reg_rtx (XFmode);
- temp = standard_80387_constant_rtx (5); /* fldl2e */
- emit_move_insn (operands[2], temp);
+
emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
})
-(define_expand "exp10sf2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:SF 1 "register_operand" "")))
- (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
- (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
- (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
- (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
- (parallel [(set (match_dup 10)
- (unspec:XF [(match_dup 9) (match_dup 5)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 11)
- (unspec:XF [(match_dup 9) (match_dup 5)]
- UNSPEC_FSCALE_EXP))])
- (set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF (match_dup 10)))]
+(define_expand "expxf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations && !optimize_size"
{
- rtx temp;
- int i;
+ operands[2] = gen_reg_rtx (XFmode);
+ emit_move_insn (operands[2], standard_80387_constant_rtx (5)); /* fldl2e */
- for (i=2; i<12; i++)
- operands[i] = gen_reg_rtx (XFmode);
- temp = standard_80387_constant_rtx (6); /* fldl2t */
- emit_move_insn (operands[3], temp);
- emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
+ emit_insn (gen_expNcorexf3 (operands[0], operands[1], operands[2]));
+ DONE;
})
-(define_expand "exp10df2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:DF 1 "register_operand" "")))
- (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
- (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
- (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
- (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
- (parallel [(set (match_dup 10)
- (unspec:XF [(match_dup 9) (match_dup 5)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 11)
- (unspec:XF [(match_dup 9) (match_dup 5)]
- UNSPEC_FSCALE_EXP))])
- (set (match_operand:DF 0 "register_operand" "")
- (float_truncate:DF (match_dup 10)))]
- "TARGET_USE_FANCY_MATH_387
- && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
+(define_expand "exp<mode>2"
+ [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+ (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations && !optimize_size"
{
- rtx temp;
- int i;
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
- for (i=2; i<12; i++)
- operands[i] = gen_reg_rtx (XFmode);
- temp = standard_80387_constant_rtx (6); /* fldl2t */
- emit_move_insn (operands[3], temp);
- emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_expxf2 (op0, op1));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
+ DONE;
})
(define_expand "exp10xf2"
- [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
- (match_dup 2)))
- (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
- (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
- (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
- (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
- (parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_dup 8) (match_dup 4)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 9)
- (unspec:XF [(match_dup 8) (match_dup 4)]
- UNSPEC_FSCALE_EXP))])]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
-{
- rtx temp;
- int i;
-
- for (i=2; i<10; i++)
- operands[i] = gen_reg_rtx (XFmode);
- temp = standard_80387_constant_rtx (6); /* fldl2t */
- emit_move_insn (operands[2], temp);
- emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
-})
-
-(define_expand "exp2sf2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:SF 1 "register_operand" "")))
- (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
- (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
- (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
- (parallel [(set (match_dup 8)
- (unspec:XF [(match_dup 7) (match_dup 3)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 9)
- (unspec:XF [(match_dup 7) (match_dup 3)]
- UNSPEC_FSCALE_EXP))])
- (set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF (match_dup 8)))]
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations && !optimize_size"
{
- int i;
+ operands[2] = gen_reg_rtx (XFmode);
+ emit_move_insn (operands[2], standard_80387_constant_rtx (6)); /* fldl2t */
- for (i=2; i<10; i++)
- operands[i] = gen_reg_rtx (XFmode);
- emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
+ emit_insn (gen_expNcorexf3 (operands[0], operands[1], operands[2]));
+ DONE;
})
-(define_expand "exp2df2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:DF 1 "register_operand" "")))
- (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
- (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
- (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
- (parallel [(set (match_dup 8)
- (unspec:XF [(match_dup 7) (match_dup 3)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 9)
- (unspec:XF [(match_dup 7) (match_dup 3)]
- UNSPEC_FSCALE_EXP))])
- (set (match_operand:DF 0 "register_operand" "")
- (float_truncate:DF (match_dup 8)))]
- "TARGET_USE_FANCY_MATH_387
- && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
+(define_expand "exp10<mode>2"
+ [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+ (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations && !optimize_size"
{
- int i;
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
- for (i=2; i<10; i++)
- operands[i] = gen_reg_rtx (XFmode);
- emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_exp10xf2 (op0, op1));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
+ DONE;
})
(define_expand "exp2xf2"
- [(set (match_dup 2) (match_operand:XF 1 "register_operand" ""))
- (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
- (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
- (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
- (parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_dup 7) (match_dup 3)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 8)
- (unspec:XF [(match_dup 7) (match_dup 3)]
- UNSPEC_FSCALE_EXP))])]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
-{
- int i;
-
- for (i=2; i<9; i++)
- operands[i] = gen_reg_rtx (XFmode);
- emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
-})
-
-(define_expand "expm1df2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:DF 1 "register_operand" "")))
- (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
- (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
- (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
- (parallel [(set (match_dup 8)
- (unspec:XF [(match_dup 7) (match_dup 5)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 9)
- (unspec:XF [(match_dup 7) (match_dup 5)]
- UNSPEC_FSCALE_EXP))])
- (parallel [(set (match_dup 11)
- (unspec:XF [(match_dup 10) (match_dup 9)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 12)
- (unspec:XF [(match_dup 10) (match_dup 9)]
- UNSPEC_FSCALE_EXP))])
- (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
- (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
- (set (match_operand:DF 0 "register_operand" "")
- (float_truncate:DF (match_dup 14)))]
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations && !optimize_size"
{
- rtx temp;
- int i;
+ operands[2] = gen_reg_rtx (XFmode);
+ emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
- for (i=2; i<15; i++)
- operands[i] = gen_reg_rtx (XFmode);
- temp = standard_80387_constant_rtx (5); /* fldl2e */
- emit_move_insn (operands[3], temp);
- emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
+ emit_insn (gen_expNcorexf3 (operands[0], operands[1], operands[2]));
+ DONE;
})
-(define_expand "expm1sf2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:SF 1 "register_operand" "")))
- (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
- (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
- (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
- (parallel [(set (match_dup 8)
- (unspec:XF [(match_dup 7) (match_dup 5)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 9)
- (unspec:XF [(match_dup 7) (match_dup 5)]
- UNSPEC_FSCALE_EXP))])
- (parallel [(set (match_dup 11)
- (unspec:XF [(match_dup 10) (match_dup 9)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 12)
- (unspec:XF [(match_dup 10) (match_dup 9)]
- UNSPEC_FSCALE_EXP))])
- (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
- (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
- (set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF (match_dup 14)))]
- "TARGET_USE_FANCY_MATH_387
- && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
+(define_expand "exp2<mode>2"
+ [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+ (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations && !optimize_size"
{
- rtx temp;
- int i;
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
- for (i=2; i<15; i++)
- operands[i] = gen_reg_rtx (XFmode);
- temp = standard_80387_constant_rtx (5); /* fldl2e */
- emit_move_insn (operands[3], temp);
- emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_exp2xf2 (op0, op1));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
+ DONE;
})
(define_expand "expm1xf2"
@@ -16761,60 +16493,30 @@
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations && !optimize_size"
{
- rtx temp;
int i;
- for (i=2; i<13; i++)
+ for (i = 2; i < 13; i++)
operands[i] = gen_reg_rtx (XFmode);
- temp = standard_80387_constant_rtx (5); /* fldl2e */
- emit_move_insn (operands[2], temp);
+
+ emit_move_insn (operands[2], standard_80387_constant_rtx (5)); /* fldl2e */
emit_move_insn (operands[9], CONST1_RTX (XFmode)); /* fld1 */
})
-(define_expand "ldexpdf3"
- [(set (match_dup 3)
- (float_extend:XF (match_operand:DF 1 "register_operand" "")))
- (set (match_dup 4)
- (float:XF (match_operand:SI 2 "register_operand" "")))
- (parallel [(set (match_dup 5)
- (unspec:XF [(match_dup 3) (match_dup 4)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 6)
- (unspec:XF [(match_dup 3) (match_dup 4)]
- UNSPEC_FSCALE_EXP))])
- (set (match_operand:DF 0 "register_operand" "")
- (float_truncate:DF (match_dup 5)))]
- "TARGET_USE_FANCY_MATH_387
- && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
-{
- int i;
-
- for (i=3; i<7; i++)
- operands[i] = gen_reg_rtx (XFmode);
-})
-
-(define_expand "ldexpsf3"
- [(set (match_dup 3)
- (float_extend:XF (match_operand:SF 1 "register_operand" "")))
- (set (match_dup 4)
- (float:XF (match_operand:SI 2 "register_operand" "")))
- (parallel [(set (match_dup 5)
- (unspec:XF [(match_dup 3) (match_dup 4)]
- UNSPEC_FSCALE_FRACT))
- (set (match_dup 6)
- (unspec:XF [(match_dup 3) (match_dup 4)]
- UNSPEC_FSCALE_EXP))])
- (set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF (match_dup 5)))]
- "TARGET_USE_FANCY_MATH_387
- && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
+(define_expand "expm1<mode>2"
+ [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+ (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations && !optimize_size"
{
- int i;
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
- for (i=3; i<7; i++)
- operands[i] = gen_reg_rtx (XFmode);
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_expm1xf2 (op0, op1));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
+ DONE;
})
(define_expand "ldexpxf3"
@@ -16830,10 +16532,26 @@
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations && !optimize_size"
{
- int i;
+ operands[3] = gen_reg_rtx (XFmode);
+ operands[4] = gen_reg_rtx (XFmode);
+})
- for (i=3; i<5; i++)
- operands[i] = gen_reg_rtx (XFmode);
+(define_expand "ldexp<mode>3"
+ [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+ (use (match_operand:X87MODEF12 1 "general_operand" ""))
+ (use (match_operand:SI 2 "register_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
+ && flag_unsafe_math_optimizations && !optimize_size"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_ldexpxf3 (op0, op1, operands[2]));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
+ DONE;
})