From c5b3a71bb105292f55f535bd5d5e0bb048c8deef Mon Sep 17 00:00:00 2001
From: drow <drow@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Wed, 5 Oct 2005 15:24:01 +0000
Subject: [PATCH] * config/arm/arm.md (insv): Use gen_int_mode in more
places.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@104997 138bc75d-0d04-0410-961f-82ee72b054a4
---
gcc/ChangeLog | 4 ++++
gcc/config/arm/arm.md | 7 ++++---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a21d4d83097e..83bc007ac088 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2005-10-05 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * config/arm/arm.md (insv): Use gen_int_mode in more places.
+
2005-10-05 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/18587
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 783fab06e8bb..b60ccb75d8fc 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1901,7 +1901,8 @@
HOST_WIDE_INT op3_value = mask & INTVAL (operands[3]);
HOST_WIDE_INT mask2 = ((mask & ~op3_value) << start_bit);
- emit_insn (gen_andsi3 (op1, operands[0], GEN_INT (~mask2)));
+ emit_insn (gen_andsi3 (op1, operands[0],
+ gen_int_mode (~mask2, SImode)));
emit_insn (gen_iorsi3 (subtarget, op1,
gen_int_mode (op3_value << start_bit, SImode)));
}
@@ -1939,7 +1940,7 @@
}
else
{
- rtx op0 = GEN_INT (mask);
+ rtx op0 = gen_int_mode (mask, SImode);
rtx op1 = gen_reg_rtx (SImode);
rtx op2 = gen_reg_rtx (SImode);
@@ -1958,7 +1959,7 @@
&& (const_ok_for_arm (mask << start_bit)
|| const_ok_for_arm (~(mask << start_bit))))
{
- op0 = GEN_INT (~(mask << start_bit));
+ op0 = gen_int_mode (~(mask << start_bit), SImode);
emit_insn (gen_andsi3 (op2, operands[0], op0));
}
else
--
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