diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d84e0f93bf580927bc59f0113691f3f9e1c5b40c..a12d12cbd7616c9abad934331aae043170317053 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2007-02-04 Kazu Hirata <kazu@codesourcery.com>
+
+ * config/m32c/bitops.md, config/m32c/jump.md,
+ config/m32c/m32c.c, config/m32c/m32c.h, config/m32r/m32r.c,
+ config/m32r/m32r.h, config/m32r/m32r.md,
+ config/m32r/predicates.md, config/m68hc11/larith.asm,
+ config/m68hc11/m68hc11.c, config/m68hc11/m68hc11.h,
+ config/m68k/m68k.h, config/mcore/mcore.md, config/mips/4k.md,
+ config/mips/mips-protos.h, config/mips/mips.c,
+ config/mips/mips.h, config/mips/mips.md, config/mips/mips16.S,
+ config/mn10300/mn10300.h, config/mn10300/predicates.md,
+ config/mt/mt.c, config/mt/mt.h, config/mt/mt.md: Follow
+ spelling conventions.
+
2007-02-03 Douglas Gregor <doug.gregor@gmail.com>
* c-opts.c (c_common_post_options): If C++0x mode is enabled, don't
diff --git a/gcc/config/m32c/bitops.md b/gcc/config/m32c/bitops.md
index 87322d386292a6f24e83b0da26b30029031d0356..33a7058e936525928e8ad9f06ecdbdedd5ab7ea1 100644
--- a/gcc/config/m32c/bitops.md
+++ b/gcc/config/m32c/bitops.md
@@ -31,7 +31,7 @@
; On the M32C, "address" for bit instructions is a regular address,
; and the bit number is stored in a separate field. Thus, we can let
; gcc do more interesting things. However, the M32C cannot set all
-; the bits in a 16 bit register, which the R8C/M16C can do.
+; the bits in a 16-bit register, which the R8C/M16C can do.
; However, it all means that we end up with two sets of patterns, one
; for each chip.
diff --git a/gcc/config/m32c/jump.md b/gcc/config/m32c/jump.md
index 5507fb465613255a420e589936e15eb1ee7fdf7a..4a358eac40fc91794359bb49573541f3af1c0909 100644
--- a/gcc/config/m32c/jump.md
+++ b/gcc/config/m32c/jump.md
@@ -27,7 +27,7 @@
(match_operand:HI 0 "register_operand" "Rhi"))]
"TARGET_A16"
; "jmpi.a\t%0"
- ; no 16 bit jmpi in r8c
+ ; no 16-bit jmpi in r8c
"push.b #0 | push.w\t%0 | rts"
[(set_attr "flags" "x")]
)
@@ -61,7 +61,7 @@
[(set_attr "flags" "n")]
)
-; No 16 bit indirect calls on r8c/m16c. */
+; No 16-bit indirect calls on r8c/m16c. */
(define_insn "call"
[(call (match_operand:QI 0 "memory_operand" "Si,SaSb,?Rmm")
(match_operand 1 "" ""))
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index b28d7473e5e2560dba4db76a8a473ef7f0cb1923..98e59dd8af7a2c0b59e6eab2eb12841c3b053f73 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -1231,7 +1231,7 @@ static struct
calls something else (because we don't know what *that* function
might do), but try to be a bit smarter if the handler is a leaf
function. We always save $a0, though, because we use that in the
- epilog to copy $fb to $sp. */
+ epilogue to copy $fb to $sp. */
static int
need_to_save (int regno)
{
@@ -1557,7 +1557,7 @@ m32c_function_arg_regno_p (int r)
}
/* HImode and PSImode are the two "native" modes as far as GCC is
- concerned, but the chips also support a 32 bit mode which is used
+ concerned, but the chips also support a 32-bit mode which is used
for some opcodes in R8C/M16C and for reset vectors and such. */
#undef TARGET_VALID_POINTER_MODE
#define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
@@ -1717,8 +1717,8 @@ m32c_initialize_trampoline (rtx tramp, rtx function, rtx chainval)
emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
emit_move_insn (A0 (HImode, 2), chainval);
emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
- /* We use 16 bit addresses here, but store the zero to turn it
- into a 24 bit offset. */
+ /* We use 16-bit addresses here, but store the zero to turn it
+ into a 24-bit offset. */
emit_move_insn (A0 (HImode, 5), function);
emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
}
@@ -1745,7 +1745,7 @@ m32c_init_libfuncs (void)
if (TARGET_A24)
{
/* We do this because the M32C has an HImode operand, but the
- M16C has an 8 bit operand. Since gcc looks at the match data
+ M16C has an 8-bit operand. Since gcc looks at the match data
and not the expanded rtl, we have to reset the array so that
the right modes are found. */
setcc_gen_code[EQ] = CODE_FOR_seq_24;
@@ -1905,12 +1905,12 @@ m32c_reg_ok_for_base_p (rtx x, int strict)
}
/* We have three choices for choosing fb->aN offsets. If we choose -128,
- we need one MOVA -128[fb],aN opcode and 16 bit aN displacements,
+ we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
like this:
EB 4B FF mova -128[$fb],$a0
D8 0C FF FF mov.w:Q #0,-1[$a0]
- Alternately, we subtract the frame size, and hopefully use 8 bit aN
+ Alternately, we subtract the frame size, and hopefully use 8-bit aN
displacements:
7B F4 stc $fb,$a0
77 54 00 01 sub #256,$a0
@@ -1922,7 +1922,7 @@ m32c_reg_ok_for_base_p (rtx x, int strict)
We have to subtract *something* so that we have a PLUS rtx to mark
that we've done this reload. The -128 offset will never result in
- an 8 bit aN offset, and the payoff for the second case is five
+ an 8-bit aN offset, and the payoff for the second case is five
loads *if* those loads are within 256 bytes of the other end of the
frame, so the third case seems best. Note that we subtract the
zero, but detect that in the addhi3 pattern. */
diff --git a/gcc/config/m32c/m32c.h b/gcc/config/m32c/m32c.h
index 1055464406736b73949a58d8adce488155d539cd..b3d5cec6613613f85d29b734c92afb0a38e684a8 100644
--- a/gcc/config/m32c/m32c.h
+++ b/gcc/config/m32c/m32c.h
@@ -29,9 +29,9 @@
#define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
/* There are four CPU series we support, but they basically break down
- into two families - the R8C/M16C families, with 16 bit address
- registers and one set of opcodes, and the M32CM/M32C group, with 24
- bit address registers and a different set of opcodes. The
+ into two families - the R8C/M16C families, with 16-bit address
+ registers and one set of opcodes, and the M32CM/M32C group, with
+ 24-bit address registers and a different set of opcodes. The
assembler doesn't care except for which opcode set is needed; the
big difference is in the memory maps, which we cover in
LIB_SPEC. */
@@ -139,7 +139,7 @@ machine_function;
GCC expects us to have a "native" format, so we pick the one that
matches "int". Pointers are 16 bits for R8C/M16C (when TARGET_A16
is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
- 24 bit pointers are stored in 32 bit words. */
+ 24-bit pointers are stored in 32-bit words. */
#define BITS_PER_UNIT 8
#define UNITS_PER_WORD 2
#define POINTER_SIZE (TARGET_A16 ? 16 : 32)
@@ -150,7 +150,7 @@ machine_function;
#define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
/* We do this because we care more about space than about speed. For
- the chips with 16 bit busses, we could set these to 16 if
+ the chips with 16-bit busses, we could set these to 16 if
desired. */
#define FUNCTION_BOUNDARY 8
#define BIGGEST_ALIGNMENT 8
@@ -180,9 +180,9 @@ machine_function;
/* Register layout:
- [r0h][r0l] $r0 (16 bits, or two 8 bit halves)
+ [r0h][r0l] $r0 (16 bits, or two 8-bit halves)
[--------] $r2 (16 bits)
- [r1h][r1l] $r1 (16 bits, or two 8 bit halves)
+ [r1h][r1l] $r1 (16 bits, or two 8-bit halves)
[--------] $r3 (16 bits)
[---][--------] $a0 (might be 24 bits)
[---][--------] $a1 (might be 24 bits)
@@ -665,7 +665,7 @@ typedef struct m32c_cumulative_args
#define STORE_FLAG_VALUE 1
-/* 16 or 24 bit pointers */
+/* 16- or 24-bit pointers */
#define Pmode (TARGET_A16 ? HImode : PSImode)
#define FUNCTION_MODE QImode
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index 9b288f319a1ecbf78b2d9c5838d88387b0aaa529..6c9f3e54d62e2e13f9a2627aaa93768f6cf918c3 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -215,7 +215,7 @@ m32r_init (void)
indexed by hard register number, and one indexed by mode. */
/* The purpose of m32r_mode_class is to shrink the range of modes so that
- they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
+ they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
mapped into one m32r_mode_class mode. */
enum m32r_mode_class
@@ -515,7 +515,7 @@ small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
return 0;
}
-/* Return 1 if OP is a symbol that can use 24 bit addressing. */
+/* Return 1 if OP is a symbol that can use 24-bit addressing. */
int
addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
@@ -550,7 +550,7 @@ addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
return 0;
}
-/* Return 1 if OP is a symbol that needs 32 bit addressing. */
+/* Return 1 if OP is a symbol that needs 32-bit addressing. */
int
addr32_operand (rtx op, enum machine_mode mode)
@@ -602,7 +602,7 @@ easy_di_const (rtx op)
split_double (op, &high_rtx, &low_rtx);
high = INTVAL (high_rtx);
low = INTVAL (low_rtx);
- /* Pick constants loadable with 2 16 bit `ldi' insns. */
+ /* Pick constants loadable with 2 16-bit `ldi' insns. */
if (high >= -128 && high <= 127
&& low >= -128 && low <= 127)
return 1;
@@ -1852,7 +1852,7 @@ m32r_print_operand (FILE * file, rtx x, int code)
Bottom halves. For symbols output arguments to a seth/add3 pair to
set Top and Bottom halves. The difference exists because for
constants seth/or3 is more readable but for symbols we need to use
- the same scheme as `ld' and `st' insns (16 bit addend is signed). */
+ the same scheme as `ld' and `st' insns (16-bit addend is signed). */
switch (GET_CODE (x))
{
case CONST_INT :
@@ -2181,7 +2181,7 @@ static void
block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
{
/* We want to pass the size as Pmode, which will normally be SImode
- but will be DImode if we are using 64 bit longs and pointers. */
+ but will be DImode if we are using 64-bit longs and pointers. */
if (GET_MODE (bytes_rtx) != VOIDmode
&& GET_MODE (bytes_rtx) != Pmode)
bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h
index b4c9ae6f4b9decc1cf34ecfc4731134ad938d4f1..637ed06ff6eea4c13f1e0e7613d30f10cbf11318 100644
--- a/gcc/config/m32r/m32r.h
+++ b/gcc/config/m32r/m32r.h
@@ -704,14 +704,14 @@ extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
This macro defines what the ranges are.
C is the letter, and VALUE is a constant value.
Return 1 if VALUE is in the range specified by C. */
-/* 'I' is used for 8 bit signed immediates.
- 'J' is used for 16 bit signed immediates.
- 'K' is used for 16 bit unsigned immediates.
- 'L' is used for 16 bit immediates left shifted by 16 (sign ???).
- 'M' is used for 24 bit unsigned immediates.
- 'N' is used for any 32 bit non-symbolic value.
- 'O' is used for 5 bit unsigned immediates (shift count).
- 'P' is used for 16 bit signed immediates for compares
+/* 'I' is used for 8-bit signed immediates.
+ 'J' is used for 16-bit signed immediates.
+ 'K' is used for 16-bit unsigned immediates.
+ 'L' is used for 16-bit immediates left shifted by 16 (sign ???).
+ 'M' is used for 24-bit unsigned immediates.
+ 'N' is used for any 32-bit non-symbolic value.
+ 'O' is used for 5-bit unsigned immediates (shift count).
+ 'P' is used for 16-bit signed immediates for compares
(values in the range -32767 to +32768). */
/* Return true if a value is inside a range. */
@@ -1135,7 +1135,7 @@ L2: .word STATIC
/* Nonzero if the constant value X is a legitimate general operand.
We don't allow (plus symbol large-constant) as the relocations can't
- describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations.
+ describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
We allow all CONST_DOUBLE's as the md file patterns will force the
constant to memory if they can't handle them. */
@@ -1580,7 +1580,7 @@ extern char m32r_punct_chars[256];
/* Specify the machine mode that pointers have.
After generation of rtl, the compiler makes no further distinction
between pointers and any other objects of this machine mode. */
-/* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
+/* ??? The M32R doesn't have full 32-bit pointers, but making this PSImode has
its own problems (you have to add extendpsisi2 and truncsipsi2).
Try to avoid it. */
#define Pmode SImode
diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md
index 2487dd893e86779f345351733fe96b74d7ca4480..a4db130ece2f0ad862ab4d26c324c3605ed26f5f 100644
--- a/gcc/config/m32r/m32r.md
+++ b/gcc/config/m32r/m32r.md
@@ -116,8 +116,8 @@
;; These fetch units are a hack to get GCC to better pack the instructions
;; for the M32Rx processor, which has two execution pipes.
;;
-;; In reality there is only one decoder, which can decode either two 16 bits
-;; instructions, or a single 32 bits instruction.
+;; In reality there is only one decoder, which can decode either two 16-bit
+;; instructions, or a single 32-bit instruction.
;;
;; Note, "fetch" models both the IF and the D pipeline stages.
;;
@@ -444,7 +444,7 @@
use 2 byte instructions wherever possible. We can assume the
constant isn't loadable with any of ldi, ld24, or seth. */
- /* See if we can load a 24 bit unsigned value and invert it. */
+ /* See if we can load a 24-bit unsigned value and invert it. */
if (UINT24_P (~ val))
{
emit_insn (gen_movsi (operands[0], GEN_INT (~ val)));
@@ -452,7 +452,7 @@
DONE;
}
- /* See if we can load a 24 bit unsigned value and shift it into place.
+ /* See if we can load a 24-bit unsigned value and shift it into place.
0x01fffffe is just beyond ld24's range. */
for (shift = 1, tmp = 0x01fffffe;
shift < 8;
@@ -488,7 +488,7 @@
;; the small data area are indexed off that. This is done for each reference
;; but cse will clean things up for us. We let the compiler choose the
;; register to use so we needn't allocate (and maybe even fix) a special
-;; register to use. Since the load and store insns have a 16 bit offset the
+;; register to use. Since the load and store insns have a 16-bit offset the
;; total size of the data area can be 64K. However, if the data area lives
;; above 16M (24 bits), _SDA_BASE_ will have to be loaded with seth/add3 which
;; would then yield 3 instructions to reference an object [though there would
@@ -531,7 +531,7 @@
[(set_attr "type" "int4")
(set_attr "length" "4")])
-;; 32 bit address support.
+;; 32-bit address support.
(define_expand "movsi_addr32"
[(set (match_dup 2)
diff --git a/gcc/config/m32r/predicates.md b/gcc/config/m32r/predicates.md
index b2426f693f6f8c3c564ab0476927fa2ab26077a8..026a3cfc8f3b46ed614d21f53354b9cb912db7f5 100644
--- a/gcc/config/m32r/predicates.md
+++ b/gcc/config/m32r/predicates.md
@@ -253,7 +253,7 @@
}
})
-;; Return true if OP is a signed 8 bit immediate value.
+;; Return true if OP is a signed 8-bit immediate value.
(define_predicate "int8_operand"
(match_code "const_int")
@@ -263,7 +263,7 @@
return INT8_P (INTVAL (op));
})
-;; Return true if OP is an unsigned 16 bit immediate value.
+;; Return true if OP is an unsigned 16-bit immediate value.
(define_predicate "uint16_operand"
(match_code "const_int")
@@ -273,7 +273,7 @@
return UINT16_P (INTVAL (op));
})
-;; Return true if OP is a register or signed 16 bit value.
+;; Return true if OP is a register or signed 16-bit value.
(define_predicate "reg_or_int16_operand"
(match_code "reg,subreg,const_int")
@@ -285,7 +285,7 @@
return INT16_P (INTVAL (op));
})
-;; Return true if OP is a register or an unsigned 16 bit value.
+;; Return true if OP is a register or an unsigned 16-bit value.
(define_predicate "reg_or_uint16_operand"
(match_code "reg,subreg,const_int")
@@ -297,7 +297,7 @@
return UINT16_P (INTVAL (op));
})
-;; Return true if OP is a register or signed 16 bit value for
+;; Return true if OP is a register or signed 16-bit value for
;; compares.
(define_predicate "reg_or_cmp_int16_operand"
@@ -330,7 +330,7 @@
return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
})
-;; Return true if OP is a signed 16 bit immediate value useful in
+;; Return true if OP is a signed 16-bit immediate value useful in
;; comparisons.
(define_predicate "cmp_int16_operand"
diff --git a/gcc/config/m68hc11/larith.asm b/gcc/config/m68hc11/larith.asm
index 64ed0797023c1c0c214e30bdeb0fef80fb160891..7bb06915fcadc49cde95b61cd1e8d870497619b6 100644
--- a/gcc/config/m68hc11/larith.asm
+++ b/gcc/config/m68hc11/larith.asm
@@ -804,7 +804,7 @@ AB_neg:
#else
#ifdef NO_TMP
;
- ; 16 bit multiplication without temp memory location.
+ ; 16-bit multiplication without temp memory location.
; (smaller but slower)
;
pshx ; (4)
diff --git a/gcc/config/m68hc11/m68hc11.c b/gcc/config/m68hc11/m68hc11.c
index 1b7069d4a169d8a73cb4f2f553da66b8091af01e..1b14284bc16534a5de9edb9f4aff92882af9fee1 100644
--- a/gcc/config/m68hc11/m68hc11.c
+++ b/gcc/config/m68hc11/m68hc11.c
@@ -382,9 +382,9 @@ create_regs_rtx (void)
}
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- - 8 bit values are stored anywhere (except the SP register).
- - 16 bit values can be stored in any register whose mode is 16
- - 32 bit values can be stored in D, X registers or in a soft register
+ - 8-bit values are stored anywhere (except the SP register).
+ - 16-bit values can be stored in any register whose mode is 16
+ - 32-bit values can be stored in D, X registers or in a soft register
(except the last one because we need 2 soft registers)
- Values whose size is > 32 bit are not stored in real hard
registers. They may be stored in soft registers if there are
diff --git a/gcc/config/m68hc11/m68hc11.h b/gcc/config/m68hc11/m68hc11.h
index a1dc509f11cdcd66697f1aae716b2d6922d2c419..2316823ca11087a9721ca0fb825a2492ccb7c824 100644
--- a/gcc/config/m68hc11/m68hc11.h
+++ b/gcc/config/m68hc11/m68hc11.h
@@ -409,9 +409,9 @@ SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31
((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE))
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- - 8 bit values are stored anywhere (except the SP register).
- - 16 bit values can be stored in any register whose mode is 16
- - 32 bit values can be stored in D, X registers or in a soft register
+ - 8-bit values are stored anywhere (except the SP register).
+ - 16-bit values can be stored in any register whose mode is 16
+ - 32-bit values can be stored in D, X registers or in a soft register
(except the last one because we need 2 soft registers)
- Values whose size is > 32 bit are not stored in real hard
registers. They may be stored in soft registers if there are
@@ -461,7 +461,7 @@ enum reg_class
D_REGS, /* 16-bit data register */
X_REGS, /* 16-bit X register */
Y_REGS, /* 16-bit Y register */
- SP_REGS, /* 16 bit stack pointer */
+ SP_REGS, /* 16-bit stack pointer */
DA_REGS, /* 8-bit A reg. */
DB_REGS, /* 8-bit B reg. */
Z_REGS, /* 16-bit fake Z register */
@@ -489,7 +489,7 @@ enum reg_class
D_OR_SP_OR_S_REGS, /* 16-bit soft register or D or SP register */
A_OR_S_REGS, /* 16-bit soft register or X, Y registers */
D_OR_A_OR_S_REGS, /* 16-bit soft register or D, X, Y registers */
- TMP_REGS, /* 16 bit fake scratch register */
+ TMP_REGS, /* 16-bit fake scratch register */
D_OR_A_OR_TMP_REGS, /* General scratch register */
G_REGS, /* 16-bit general register
(H_REGS + soft registers) */
diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h
index e1b508e4b45ba024c5aa816af1d09aba4bbe6a97..39a5878089714f1f208389ac254cc11b363cc7c2 100644
--- a/gcc/config/m68k/m68k.h
+++ b/gcc/config/m68k/m68k.h
@@ -288,7 +288,7 @@ Boston, MA 02110-1301, USA. */
#define PREFERRED_STACK_BOUNDARY (TARGET_COLDFIRE ? 32 : 16)
/* No data type wants to be aligned rounder than this.
- Most published ABIs say that ints should be aligned on 16 bit
+ Most published ABIs say that ints should be aligned on 16-bit
boundaries, but CPUs with 32-bit busses get better performance
aligned on 32-bit boundaries. ColdFires without a misalignment
module require 32-bit alignment. */
@@ -918,7 +918,7 @@ __transfer_from_trampoline () \
|| (INTVAL (XEXP (X, 1)) == 8 \
&& (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))))
-/* Coldfire FPU only accepts addressing modes 2-5 */
+/* ColdFire FPU only accepts addressing modes 2-5. */
#define GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ if (LEGITIMATE_BASE_REG_P (X) \
|| ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index c4af69ed0d35efd1539f6fcb76a226f422d735b7..5be6dc036d8b67c07cf7d1c298756edf44d1dc08 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -2657,7 +2657,7 @@
{
if (INTVAL (operands[2]) == 8 && INTVAL (operands[3]) % 8 == 0)
{
- /* 8 bit field, aligned properly, use the xtrb[0123]+sext sequence. */
+ /* 8-bit field, aligned properly, use the xtrb[0123]+sext sequence. */
/* not DONE, not FAIL, but let the RTL get generated.... */
}
else if (TARGET_W_FIELD)
@@ -2694,7 +2694,7 @@
{
if (INTVAL (operands[2]) == 8 && INTVAL (operands[3]) % 8 == 0)
{
- /* 8 bit field, aligned properly, use the xtrb[0123] sequence. */
+ /* 8-bit field, aligned properly, use the xtrb[0123] sequence. */
/* Let the template generate some RTL.... */
}
else if (CONST_OK_FOR_K ((1 << INTVAL (operands[2])) - 1))
diff --git a/gcc/config/mips/4k.md b/gcc/config/mips/4k.md
index 6f7d6d1d97970ec6dea4acfe7508e7cb7ef26730..8e660934ef8ab34f9e1335128472aaaf3f642054 100644
--- a/gcc/config/mips/4k.md
+++ b/gcc/config/mips/4k.md
@@ -51,8 +51,8 @@
"r4k_ixu_arith")
;; 4Kc/4Km
-;; unsigned divide - 8/16/24/32 bit operand have latencies 9/17/25/33
-;; signed divide - 8/16/24/32 bit operand have latencies 10/18/26/34
+;; unsigned divide - 8/16/24/32-bit operand have latencies 9/17/25/33
+;; signed divide - 8/16/24/32-bit operand have latencies 10/18/26/34
(define_insn_reservation "r4k_idiv_4kc" 34
(and (eq_attr "cpu" "4kc")
(and (eq_attr "type" "idiv")
diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index e5716da4d03a7c81bd36ec9dbb3c16dbc4e06f2d..a9fa42ee8159076523cbfbf7954f80f80bcea015 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -3,7 +3,7 @@
1999, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
Contributed by A. Lichnewsky (lich@inria.inria.fr).
Changed by Michael Meissner (meissner@osf.org).
- 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
+ 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
Brendan Eich (brendan@microunity.com).
This file is part of GCC.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 1f8a56c057aab0340f5915027999d13f79ced1fb..93c482368ae2b2b05ee94c6ed5713e41a7620b19 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -3,7 +3,7 @@
1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
Contributed by A. Lichnewsky, lich@inria.inria.fr.
Changes by Michael Meissner, meissner@osf.org.
- 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
+ 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
Brendan Eich, brendan@microunity.com.
This file is part of GCC.
@@ -2522,7 +2522,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
return true;
}
- /* We can use cmpi for an xor with an unsigned 16 bit value. */
+ /* We can use cmpi for an xor with an unsigned 16-bit value. */
if ((outer_code) == XOR
&& INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
{
@@ -2531,7 +2531,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
}
/* We may be able to use slt or sltu for a comparison with a
- signed 16 bit value. (The boundary conditions aren't quite
+ signed 16-bit value. (The boundary conditions aren't quite
right, but this is just a heuristic anyhow.) */
if (((outer_code) == LT || (outer_code) == LE
|| (outer_code) == GE || (outer_code) == GT
@@ -2706,7 +2706,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
return true;
case SIGN_EXTEND:
- /* A sign extend from SImode to DImode in 64 bit mode is often
+ /* A sign extend from SImode to DImode in 64-bit mode is often
zero instructions, because the result can often be used
directly by another instruction; we'll call it one. */
if (TARGET_64BIT && mode == DImode
@@ -2960,7 +2960,7 @@ mips_output_move (rtx dest, rtx src)
if (src_code == CONST_INT)
{
/* Don't use the X format, because that will give out of
- range numbers for 64 bit hosts and 32 bit targets. */
+ range numbers for 64-bit hosts and 32-bit targets. */
if (!TARGET_MIPS16)
return "li\t%0,%1\t\t\t# %X1";
@@ -3888,8 +3888,8 @@ function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
&& host_integerp (TYPE_SIZE_UNIT (type), 1)
&& named)
{
- /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
- structure contains a double in its entirety, then that 64 bit
+ /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
+ structure contains a double in its entirety, then that 64-bit
chunk is passed in a floating point register. */
tree field;
@@ -3905,7 +3905,7 @@ function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
if (field != 0)
{
/* Now handle the special case by returning a PARALLEL
- indicating where each 64 bit chunk goes. INFO.REG_WORDS
+ indicating where each 64-bit chunk goes. INFO.REG_WORDS
chunks are passed in registers. */
unsigned int i;
HOST_WIDE_INT bitpos;
@@ -6541,7 +6541,7 @@ mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
/* Save registers starting from high to low. The debuggers prefer at least
the return register be stored at func+4, and also it allows us not to
- need a nop in the epilog if at least one register is reloaded in
+ need a nop in the epilogue if at least one register is reloaded in
addition to return address. */
offset = cfun->machine->frame.gp_sp_offset - sp_offset;
for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
@@ -6645,8 +6645,8 @@ mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
#endif
/* In mips16 mode, we may need to generate a 32 bit to handle
- floating point arguments. The linker will arrange for any 32 bit
- functions to call this stub, which will then jump to the 16 bit
+ floating point arguments. The linker will arrange for any 32-bit
+ functions to call this stub, which will then jump to the 16-bit
function proper. */
if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
&& current_function_args_info.fp_code != 0)
@@ -7895,7 +7895,7 @@ mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
int gparg, fparg;
unsigned int f;
- /* This code only works for the original 32 bit ABI and the O64 ABI. */
+ /* This code only works for the original 32-bit ABI and the O64 ABI. */
gcc_assert (TARGET_OLDABI);
if (from_fp_p)
@@ -7943,9 +7943,9 @@ mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
}
/* Build a mips16 function stub. This is used for functions which
- take arguments in the floating point registers. It is 32 bit code
+ take arguments in the floating point registers. It is 32-bit code
that moves the floating point args into the general registers, and
- then jumps to the 16 bit code. */
+ then jumps to the 16-bit code. */
static void
build_mips16_function_stub (FILE *file)
@@ -8040,11 +8040,11 @@ static struct mips16_stub *mips16_stubs;
/* Build a call stub for a mips16 call. A stub is needed if we are
passing any floating point values which should go into the floating
- point registers. If we are, and the call turns out to be to a 32
- bit function, the stub will be used to move the values into the
- floating point registers before calling the 32 bit function. The
- linker will magically adjust the function call to either the 16 bit
- function or the 32 bit stub, depending upon where the function call
+ point registers. If we are, and the call turns out to be to a
+ 32-bit function, the stub will be used to move the values into the
+ floating point registers before calling the 32-bit function. The
+ linker will magically adjust the function call to either the 16-bit
+ function or the 32-bit stub, depending upon where the function call
is actually defined.
Similarly, we need a stub if the return value might come back in a
@@ -8164,7 +8164,7 @@ build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
{
/* Build a special purpose stub. When the linker sees a
function call in mips16 code, it will check where the target
- is defined. If the target is a 32 bit call, the linker will
+ is defined. If the target is a 32-bit call, the linker will
search for the section defined here. It can tell which
symbol this section is associated with by looking at the
relocation information (the name is unreliable, since this
@@ -8223,7 +8223,7 @@ build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
}
/* We build the stub code by hand. That's the only way we can
- do it, since we can't generate 32 bit code during a 16 bit
+ do it, since we can't generate 32-bit code during a 16-bit
compilation. */
/* We don't want the assembler to insert any nops here. */
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index f01349bb0db6c621a625428d1b168bde6bd64805..de926be4fd8fdfe6f22e525ea047b4633736825b 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -3,7 +3,7 @@
1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
Contributed by A. Lichnewsky (lich@inria.inria.fr).
Changed by Michael Meissner (meissner@osf.org).
- 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
+ 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
Brendan Eich (brendan@microunity.com).
This file is part of GCC.
@@ -83,7 +83,7 @@ struct mips_rtx_cost_data
/* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
- to work on a 64 bit machine. */
+ to work on a 64-bit machine. */
#define ABI_32 0
#define ABI_N32 1
@@ -96,7 +96,7 @@ struct mips_rtx_cost_data
struct mips_cpu_info {
/* The 'canonical' name of the processor as far as GCC is concerned.
It's typically a manufacturer's prefix followed by a numerical
- designation. It should be lower case. */
+ designation. It should be lowercase. */
const char *name;
/* The internal processor number that most closely matches this
@@ -566,7 +566,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
ABI for which this is true. */
#define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
-/* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
+/* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
|| ISA_MIPS4 \
|| ISA_MIPS64)
@@ -704,7 +704,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
#define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
&& !TARGET_MIPS16)
-/* ISA has instructions for accessing top part of 64 bit fp regs */
+/* ISA has instructions for accessing top part of 64-bit fp regs. */
#define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
/* True if the result of a load is not available to the next instruction.
@@ -1123,7 +1123,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
-/* When in 64 bit mode, move insns will sign extend SImode and CCmode
+/* When in 64-bit mode, move insns will sign extend SImode and CCmode
moves. All other references are zero extended. */
#define LOAD_EXTEND_OP(MODE) \
(TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
@@ -1893,8 +1893,8 @@ typedef struct mips_args {
/* On the mips16, we need to keep track of which floating point
arguments were passed in general registers, but would have been
- passed in the FP regs if this were a 32 bit function, so that we
- can move them to the FP regs if we wind up calling a 32 bit
+ passed in the FP regs if this were a 32-bit function, so that we
+ can move them to the FP regs if we wind up calling a 32-bit
function. We record this information in fp_code, encoded in base
four. A zero digit means no floating point argument, a one digit
means an SFmode argument, and a two digit means a DFmode argument,
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index b175fb343e8f3bb4448337c4d483ca130fcb82f7..a14b449a11dba1ba07fd4d5488d7164739c94247 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -3,7 +3,7 @@
;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
;; Contributed by A. Lichnewsky, lich@inria.inria.fr
;; Changes by Michael Meissner, meissner@osf.org
-;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
+;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
;; Brendan Eich, brendan@microunity.com.
;; This file is part of GCC.
@@ -1699,8 +1699,8 @@
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
-;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
-;; instruction. The HI/LO registers are used as a 64 bit accumulator.
+;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
+;; instruction. The HI/LO registers are used as a 64-bit accumulator.
(define_insn "madsi"
[(set (match_operand:SI 0 "register_operand" "+l")
@@ -3533,8 +3533,8 @@
;; the sum of two general registers. We use two versions for each of
;; these four instructions: one where the two general registers are
;; SImode, and one where they are DImode. This is because general
-;; registers will be in SImode when they hold 32 bit values, but,
-;; since the 32 bit values are always sign extended, the [ls][wd]xc1
+;; registers will be in SImode when they hold 32-bit values, but,
+;; since the 32-bit values are always sign extended, the [ls][wd]xc1
;; instructions will still work correctly.
;; ??? Perhaps it would be better to support these instructions by
diff --git a/gcc/config/mips/mips16.S b/gcc/config/mips/mips16.S
index a6afa0c0544791cd997ba8aab30cb289d4cde381..5894a862f5cd20cb79cdb577fa4028bb4d66d107 100644
--- a/gcc/config/mips/mips16.S
+++ b/gcc/config/mips/mips16.S
@@ -38,7 +38,7 @@ Boston, MA 02110-1301, USA. */
values using the soft-float calling convention, but do the actual
operation using the hard floating point instructions. */
-/* This file contains 32 bit assembly code. */
+/* This file contains 32-bit assembly code. */
.set nomips16
/* Start a function. */
@@ -185,8 +185,8 @@ STARTFN (__mips16_fix_truncsfsi)
/* The double precision operations. We need to use different code
based on the preprocessor symbol __mips64, because the way in which
double precision values will change. Without __mips64, the value
- is passed in two 32 bit registers. With __mips64, the value is
- passed in a single 64 bit register. */
+ is passed in two 32-bit registers. With __mips64, the value is
+ passed in a single 64-bit register. */
/* Load the first double precision operand. */
@@ -425,7 +425,7 @@ STARTFN (__mips16_ret_df)
#endif
#endif /* !__mips_single_float */
-/* These functions are used by 16 bit code when calling via a function
+/* These functions are used by 16-bit code when calling via a function
pointer. They must copy the floating point arguments from the gp
regs into the fp regs. The function to call will be in $2. The
exact set of floating point arguments to copy is encoded in the
@@ -511,7 +511,7 @@ STARTFN (__mips16_call_stub_10)
to use it to hold the return address.
Note that we do not know whether the function we are calling is 16
- bit or 32 bit. However, it does not matter, because 16 bit
+ bit or 32 bit. However, it does not matter, because 16-bit
functions always return floating point values in both the gp and
the fp regs. It would be possible to check whether the function
being called is 16 bits, in which case the copy is unnecessary;
diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h
index 6c51152248d071172031f52d48f8e594ce351242..f91db27aaff2bb7e2be24d26d287b2e8c440bb7d 100644
--- a/gcc/config/mn10300/mn10300.h
+++ b/gcc/config/mn10300/mn10300.h
@@ -90,7 +90,7 @@ extern enum processor_type mn10300_processor;
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
#define PARM_BOUNDARY 32
-/* The stack goes in 32 bit lumps. */
+/* The stack goes in 32-bit lumps. */
#define STACK_BOUNDARY 32
/* Allocation boundary (in *bits*) for the code of a function.
diff --git a/gcc/config/mn10300/predicates.md b/gcc/config/mn10300/predicates.md
index b8d3bfad75bffca98cc929e04e87b501cfa6c9d7..096e0b7ef8e1b19a9c875f9b99e1369253f57cab 100644
--- a/gcc/config/mn10300/predicates.md
+++ b/gcc/config/mn10300/predicates.md
@@ -28,7 +28,7 @@
;; Return 1 if X is a CONST_INT that is only 8 bits wide. This is
;; used for the btst insn which may examine memory or a register (the
-;; memory variant only allows an unsigned 8 bit integer).
+;; memory variant only allows an unsigned 8-bit integer).
(define_predicate "const_8bit_operand"
(match_code "const_int")
diff --git a/gcc/config/mt/mt.c b/gcc/config/mt/mt.c
index 44c494ee99e09edbba9889ed708985a20828eaab..df5d8f286b29360477a8c55c36a3ec20bb2ddad7 100644
--- a/gcc/config/mt/mt.c
+++ b/gcc/config/mt/mt.c
@@ -701,7 +701,7 @@ mt_legitimate_address_p (enum machine_mode mode, rtx xinsn, int strict)
}
/* Return truth value of whether OP can be used as an operands where a
- register or 16 bit unsigned integer is needed. */
+ register or 16-bit unsigned integer is needed. */
int
uns_arith_operand (rtx op, enum machine_mode mode)
@@ -713,7 +713,7 @@ uns_arith_operand (rtx op, enum machine_mode mode)
}
/* Return truth value of whether OP can be used as an operands where a
- 16 bit integer is needed. */
+ 16-bit integer is needed. */
int
arith_operand (rtx op, enum machine_mode mode)
diff --git a/gcc/config/mt/mt.h b/gcc/config/mt/mt.h
index 90d98ac47dced4b9e3d5d48c70f97a798b5cf550..79d94d451c3d363d3a322509549b25e23f81ab9e 100644
--- a/gcc/config/mt/mt.h
+++ b/gcc/config/mt/mt.h
@@ -346,12 +346,12 @@ enum reg_class
/* For MorphoRISC1:
`I' is used for the range of constants an arithmetic insn can
- actually contain (16 bits signed integers).
+ actually contain (16-bit signed integers).
`J' is used for the range which is just zero (ie, $r0).
`K' is used for the range of constants a logical insn can actually
- contain (16 bit zero-extended integers).
+ contain (16-bit zero-extended integers).
`L' is used for the range of constants that be loaded with lui
(ie, the bottom 16 bits are zero).
@@ -359,11 +359,11 @@ enum reg_class
`M' is used for the range of constants that take two words to load
(ie, not matched by `I', `K', and `L').
- `N' is used for negative 16 bit constants other than -65536.
+ `N' is used for negative 16-bit constants other than -65536.
- `O' is a 15 bit signed integer.
+ `O' is a 15-bit signed integer.
- `P' is used for positive 16 bit constants. */
+ `P' is used for positive 16-bit constants. */
#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
#define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
diff --git a/gcc/config/mt/mt.md b/gcc/config/mt/mt.md
index fd244386ccd4584e38ae495e4be2109eb37c33e1..0082f7a597ca073e85ec11ad3a7d211dc80b31f0 100644
--- a/gcc/config/mt/mt.md
+++ b/gcc/config/mt/mt.md
@@ -865,7 +865,7 @@
}")
-;; 32 bit Integer arithmetic
+;; 32-bit Integer arithmetic
;; Addition
(define_insn "addsi3"
@@ -903,7 +903,7 @@
(set_attr "type" "arith,arith")])
-;; 32 bit Integer Shifts and Rotates
+;; 32-bit Integer Shifts and Rotates
;; Arithmetic Shift Left
(define_insn "ashlsi3"
@@ -942,9 +942,9 @@
(set_attr "type" "arith,arith")])
-;; 32 Bit Integer Logical operations
+;; 32-Bit Integer Logical operations
-;; Logical AND, 32 bit integers
+;; Logical AND, 32-bit integers
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(and:SI (match_operand:SI 1 "register_operand" "%r,r")
@@ -956,7 +956,7 @@
[(set_attr "length" "4,4")
(set_attr "type" "arith,arith")])
-;; Inclusive OR, 32 bit integers
+;; Inclusive OR, 32-bit integers
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ior:SI (match_operand:SI 1 "register_operand" "%r,r")
@@ -968,7 +968,7 @@
[(set_attr "length" "4,4")
(set_attr "type" "arith,arith")])
-;; Exclusive OR, 32 bit integers
+;; Exclusive OR, 32-bit integers
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(xor:SI (match_operand:SI 1 "register_operand" "%r,r")
@@ -981,7 +981,7 @@
(set_attr "type" "arith,arith")])
-;; One's complement, 32 bit integers
+;; One's complement, 32-bit integers
(define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "r")))]