From cd36b2c0e14e6a32b9ed41d460d1c330f2775894 Mon Sep 17 00:00:00 2001
From: bernds <bernds@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Tue, 21 Nov 2006 12:07:39 +0000
Subject: [PATCH] * config/bfin/bfin.c (hard_regno_mode_ok): Only allow
first 31 regs for DImode. (bfin_register_move_cost): Bump costs
if trying to move plain integer values through accumulators.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@119055 138bc75d-0d04-0410-961f-82ee72b054a4
---
gcc/ChangeLog | 5 +++++
gcc/config/bfin/bfin.c | 19 +++++++++++++++++--
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a7f0b779db4d..99b91c0a9b9f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -9,6 +9,11 @@
(add_to_reg): Renamed from add_to_sp. All callers changed. Lose some
dead code.
+ * config/bfin/bfin.c (hard_regno_mode_ok): Only allow first 31
+ regs for DImode.
+ (bfin_register_move_cost): Bump costs if trying to move plain
+ integer values through accumulators.
+
2006-11-21 Ben Elliston <bje@au.ibm.com>
* config/spu/spu.c (spu_expand_vector_init): Initialise x.
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index 46c028b53f8f..10ccda2d99b6 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -1854,10 +1854,16 @@ hard_regno_mode_ok (int regno, enum machine_mode mode)
return mode == BImode;
if (mode == PDImode || mode == V2PDImode)
return regno == REG_A0 || regno == REG_A1;
+
+ /* Allow all normal 32 bit regs, except REG_M3, in case regclass ever comes
+ up with a bad register class (such as ALL_REGS) for DImode. */
+ if (mode == DImode)
+ return regno < REG_M3;
+
if (mode == SImode
&& TEST_HARD_REG_BIT (reg_class_contents[PROLOGUE_REGS], regno))
return 1;
-
+
return TEST_HARD_REG_BIT (reg_class_contents[MOST_REGS], regno);
}
@@ -1873,7 +1879,7 @@ bfin_vector_mode_supported_p (enum machine_mode mode)
one in class CLASS2. A cost of 2 is the default. */
int
-bfin_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
+bfin_register_move_cost (enum machine_mode mode,
enum reg_class class1, enum reg_class class2)
{
/* These need secondary reloads, so they're more expensive. */
@@ -1891,6 +1897,15 @@ bfin_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
if (class1 == DREGS && class2 != DREGS)
return 2 * 2;
+ if (GET_MODE_CLASS (mode) == MODE_INT)
+ {
+ /* Discourage trying to use the accumulators. */
+ if (TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A0)
+ || TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A1)
+ || TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A0)
+ || TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A1))
+ return 20;
+ }
return 2;
}
--
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