pubpm:Mmio<u8>,// Port multiplier, 1: Command, 0: Control
pubcommand:Mmio<u8>,// Command register
pubfeaturel:Mmio<u8>,// Feature register, 7:0
// DWORD 1
publba0:Mmio<u8>,// LBA low register, 7:0
publba1:Mmio<u8>,// LBA mid register, 15:8
publba2:Mmio<u8>,// LBA high register, 23:16
pubdevice:Mmio<u8>,// Device register
// DWORD 2
publba3:Mmio<u8>,// LBA register, 31:24
publba4:Mmio<u8>,// LBA register, 39:32
publba5:Mmio<u8>,// LBA register, 47:40
pubfeatureh:Mmio<u8>,// Feature register, 15:8
// DWORD 3
pubcountl:Mmio<u8>,// Count register, 7:0
pubcounth:Mmio<u8>,// Count register, 15:8
pubicc:Mmio<u8>,// Isochronous command completion
pubcontrol:Mmio<u8>,// Control register
// DWORD 4
pubrsv1:[Mmio<u8>;4],// Reserved
}
#[repr(packed)]
pubstructFisRegD2H{
// DWORD 0
pubfis_type:Mmio<u8>,// FIS_TYPE_REG_D2H
pubpm:Mmio<u8>,// Port multiplier, Interrupt bit: 2
pubstatus:Mmio<u8>,// Status register
puberror:Mmio<u8>,// Error register
// DWORD 1
publba0:Mmio<u8>,// LBA low register, 7:0
publba1:Mmio<u8>,// LBA mid register, 15:8
publba2:Mmio<u8>,// LBA high register, 23:16
pubdevice:Mmio<u8>,// Device register
// DWORD 2
publba3:Mmio<u8>,// LBA register, 31:24
publba4:Mmio<u8>,// LBA register, 39:32
publba5:Mmio<u8>,// LBA register, 47:40
pubrsv2:Mmio<u8>,// Reserved
// DWORD 3
pubcountl:Mmio<u8>,// Count register, 7:0
pubcounth:Mmio<u8>,// Count register, 15:8
pubrsv3:[Mmio<u8>;2],// Reserved
// DWORD 4
pubrsv4:[Mmio<u8>;4],// Reserved
}
#[repr(packed)]
pubstructFisData{
// DWORD 0
pubfis_type:Mmio<u8>,// FIS_TYPE_DATA
pubpm:Mmio<u8>,// Port multiplier
pubrsv1:[Mmio<u8>;2],// Reserved
// DWORD 1 ~ N
pubdata:[Mmio<u8>;252],// Payload
}
#[repr(packed)]
pubstructFisPioSetup{
// DWORD 0
pubfis_type:Mmio<u8>,// FIS_TYPE_PIO_SETUP
pubpm:Mmio<u8>,// Port multiplier, direction: 4 - device to host, interrupt: 2
pubstatus:Mmio<u8>,// Status register
puberror:Mmio<u8>,// Error register
// DWORD 1
publba0:Mmio<u8>,// LBA low register, 7:0
publba1:Mmio<u8>,// LBA mid register, 15:8
publba2:Mmio<u8>,// LBA high register, 23:16
pubdevice:Mmio<u8>,// Device register
// DWORD 2
publba3:Mmio<u8>,// LBA register, 31:24
publba4:Mmio<u8>,// LBA register, 39:32
publba5:Mmio<u8>,// LBA register, 47:40
pubrsv2:Mmio<u8>,// Reserved
// DWORD 3
pubcountl:Mmio<u8>,// Count register, 7:0
pubcounth:Mmio<u8>,// Count register, 15:8
pubrsv3:Mmio<u8>,// Reserved
pube_status:Mmio<u8>,// New value of status register
// DWORD 4
pubtc:Mmio<u16>,// Transfer count
pubrsv4:[Mmio<u8>;2],// Reserved
}
#[repr(packed)]
pubstructFisDmaSetup{
// DWORD 0
pubfis_type:Mmio<u8>,// FIS_TYPE_DMA_SETUP
pubpm:Mmio<u8>,// Port multiplier, direction: 4 - device to host, interrupt: 2, auto-activate: 1
pubrsv1:[Mmio<u8>;2],// Reserved
// DWORD 1&2
pubdma_buffer_id:Mmio<u64>,/* DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work. */
// DWORD 3
pubrsv3:Mmio<u32>,// More reserved
// DWORD 4
pubdma_buffer_offset:Mmio<u32>,// Byte offset into buffer. First 2 bits must be 0
// DWORD 5
pubtransfer_count:Mmio<u32>,// Number of bytes to transfer. Bit 0 must be 0