Commit b18653c5 authored by Jeremy Soller's avatar Jeremy Soller

Debug all driver activity to display:1, use format to avoid line splitting

parent 5724bacd
......@@ -191,8 +191,8 @@ impl HbaPort {
48
};
println!(" + Serial: {} Firmware: {} Model: {} {}-bit LBA Size: {} MB",
serial.trim(), firmware.trim(), model.trim(), lba_bits, sectors / 2048);
print!("{}", format!(" + Serial: {} Firmware: {} Model: {} {}-bit LBA Size: {} MB\n",
serial.trim(), firmware.trim(), model.trim(), lba_bits, sectors / 2048));
Some(sectors * 512)
} else {
......@@ -230,7 +230,7 @@ impl HbaPort {
}
pub fn ata_dma(&mut self, block: u64, sectors: usize, write: bool, clb: &mut Dma<[HbaCmdHeader; 32]>, ctbas: &mut [Dma<HbaCmdTable>; 32], buf: &mut Dma<[u8; 256 * 512]>) -> Result<usize> {
//println!("AHCI {:X} DMA BLOCK: {:X} SECTORS: {} WRITE: {}", (self as *mut HbaPort) as usize, block, sectors, write);
//print!("{}", format!("AHCI {:X} DMA BLOCK: {:X} SECTORS: {} WRITE: {}\n", (self as *mut HbaPort) as usize, block, sectors, write));
assert!(sectors > 0 && sectors < 256);
......@@ -286,20 +286,20 @@ impl HbaPort {
while self.ci.readf(1 << slot) {
if self.is.readf(HBA_PORT_IS_TFES) {
println!("IS_TFES set in CI loop TFS {:X} SERR {:X}", self.tfd.read(), self.serr.read());
print!("{}", format!("IS_TFES set in CI loop TFS {:X} SERR {:X}\n", self.tfd.read(), self.serr.read()));
return Err(Error::new(EIO));
}
pause();
}
if self.is.readf(HBA_PORT_IS_TFES) {
println!("IS_TFES set after CI loop TFS {:X} SERR {:X}", self.tfd.read(), self.serr.read());
print!("{}", format!("IS_TFES set after CI loop TFS {:X} SERR {:X}\n", self.tfd.read(), self.serr.read()));
return Err(Error::new(EIO));
}
Ok(sectors * 512)
} else {
println!("No Command Slots");
print!("No Command Slots\n");
Err(Error::new(EIO))
}
}
......
......@@ -8,21 +8,19 @@ pub mod fis;
pub mod hba;
pub fn disks(base: usize, irq: u8) -> Vec<Disk> {
println!(" + AHCI on: {:X} IRQ: {}", base as usize, irq);
let pi = unsafe { &mut *(base as *mut HbaMem) }.pi.read();
let ret: Vec<Disk> = (0..32)
.filter(|&i| pi & 1 << i as i32 == 1 << i as i32)
.filter_map(|i| {
let port = &mut unsafe { &mut *(base as *mut HbaMem) }.ports[i];
let port_type = port.probe();
println!("{}: {:?}", i, port_type);
print!("{}", format!("{}: {:?}\n", i, port_type));
match port_type {
HbaPortType::SATA => {
match Disk::new(i, port) {
Ok(disk) => Some(disk),
Err(err) => {
println!("{}: {}", i, err);
print!("{}", format!("{}: {}\n", i, err));
None
}
}
......
......@@ -27,6 +27,8 @@ fn main() {
let irq_str = args.next().expect("ahcid: no irq provided");
let irq = irq_str.parse::<u8>().expect("ahcid: failed to parse irq");
print!("{}", format!(" + AHCI on: {:X} IRQ: {}\n", bar, irq));
thread::spawn(move || {
unsafe {
syscall::iopl(3).expect("ahcid: failed to get I/O permission");
......
......@@ -93,7 +93,6 @@ const TD_DD: u8 = 1;
pub struct Intel8254x {
base: usize,
irq: u8,
receive_buffer: [Dma<[u8; 16384]>; 16],
receive_ring: Dma<[Rd; 16]>,
transmit_buffer: [Dma<[u8; 16384]>; 16],
......@@ -201,10 +200,9 @@ impl Scheme for Intel8254x {
}
impl Intel8254x {
pub unsafe fn new(base: usize, irq: u8) -> Result<Self> {
pub unsafe fn new(base: usize) -> Result<Self> {
let mut module = Intel8254x {
base: base,
irq: irq,
receive_buffer: [Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?,
Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?,
Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?,
......@@ -245,8 +243,6 @@ impl Intel8254x {
}
pub unsafe fn init(&mut self) {
println!(" + Intel 8254x on: {:X}, IRQ: {}", self.base, self.irq);
// Enable auto negotiate, link, clear reset, do not Invert Loss-Of Signal
self.flag(CTRL, CTRL_ASDE | CTRL_SLU, true);
self.flag(CTRL, CTRL_LRST, false);
......@@ -272,7 +268,7 @@ impl Intel8254x {
(mac_low >> 24) as u8,
mac_high as u8,
(mac_high >> 8) as u8];
println!(" - MAC: {:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
print!("{}", format!(" - MAC: {:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]));
let _ = setcfg("mac", &format!("{:>02X}.{:>02X}.{:>02X}.{:>02X}.{:>02X}.{:>02X}", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]));
//
......
......@@ -27,6 +27,8 @@ fn main() {
let irq_str = args.next().expect("e1000d: no irq provided");
let irq = irq_str.parse::<u8>().expect("e1000d: failed to parse irq");
print!("{}", format!(" + E1000 on: {:X}, IRQ: {}\n", bar, irq));
thread::spawn(move || {
unsafe {
syscall::iopl(3).expect("e1000d: failed to get I/O permission");
......@@ -38,7 +40,7 @@ fn main() {
let address = unsafe { syscall::physmap(bar, 128*1024, MAP_WRITE).expect("e1000d: failed to map address") };
{
let device = Arc::new(unsafe { device::Intel8254x::new(address, irq).expect("e1000d: failed to allocate device") });
let device = Arc::new(unsafe { device::Intel8254x::new(address).expect("e1000d: failed to allocate device") });
let mut event_queue = EventQueue::<usize>::new().expect("e1000d: failed to create event queue");
......
......@@ -31,43 +31,44 @@ fn main() {
unsafe { iopl(3).unwrap() };
println!("PCI BS/DV/FN VEND:DEVI CL.SC.IN.RV");
print!("PCI BS/DV/FN VEND:DEVI CL.SC.IN.RV\n");
let pci = Pci::new();
for bus in pci.buses() {
for dev in bus.devs() {
for func in dev.funcs() {
if let Some(header) = func.header() {
print!("PCI {:>02X}/{:>02X}/{:>02X} {:>04X}:{:>04X} {:>02X}.{:>02X}.{:>02X}.{:>02X}",
let pci_class = PciClass::from(header.class);
let mut string = format!("PCI {:>02X}/{:>02X}/{:>02X} {:>04X}:{:>04X} {:>02X}.{:>02X}.{:>02X}.{:>02X} {:?}",
bus.num, dev.num, func.num,
header.vendor_id, header.device_id,
header.class, header.subclass, header.interface, header.revision);
header.class, header.subclass, header.interface, header.revision,
pci_class);
let pci_class = PciClass::from(header.class);
print!(" {:?}", pci_class);
match pci_class {
PciClass::Storage => match header.subclass {
0x01 => {
print!(" IDE");
string.push_str(" IDE");
},
0x06 => {
print!(" SATA");
string.push_str(" SATA");
},
_ => ()
},
PciClass::SerialBus => match header.subclass {
0x03 => match header.interface {
0x00 => {
print!(" UHCI");
string.push_str(" UHCI");
},
0x10 => {
print!(" OHCI");
string.push_str(" OHCI");
},
0x20 => {
print!(" EHCI");
string.push_str(" EHCI");
},
0x30 => {
print!(" XHCI");
string.push_str(" XHCI");
},
_ => ()
},
......@@ -79,12 +80,14 @@ fn main() {
for i in 0..header.bars.len() {
match PciBar::from(header.bars[i]) {
PciBar::None => (),
PciBar::Memory(address) => print!(" {}={:>08X}", i, address),
PciBar::Port(address) => print!(" {}={:>04X}", i, address)
PciBar::Memory(address) => string.push_str(&format!(" {}={:>08X}", i, address)),
PciBar::Port(address) => string.push_str(&format!(" {}={:>04X}", i, address))
}
}
print!("\n");
string.push('\n');
print!("{}", string);
for driver in config.drivers.iter() {
if let Some(class) = driver.class {
......
......@@ -66,7 +66,6 @@ struct Td {
pub struct Rtl8168 {
regs: &'static mut Regs,
irq: u8,
receive_buffer: [Dma<[u8; 0x1FF8]>; 16],
receive_ring: Dma<[Rd; 16]>,
transmit_buffer: [Dma<[u8; 7552]>; 16],
......@@ -89,13 +88,10 @@ impl SchemeMut for Rtl8168 {
}
fn read(&mut self, _id: usize, buf: &mut [u8]) -> Result<usize> {
println!("Try Receive {}", buf.len());
for (rd_i, rd) in self.receive_ring.iter_mut().enumerate() {
if ! rd.ctrl.readf(OWN) {
let rd_len = rd.ctrl.read() & 0x3FFF;
println!("Receive {}: {}", rd_i, rd_len);
let data = &self.receive_buffer[rd_i as usize];
let mut i = 0;
......@@ -115,11 +111,9 @@ impl SchemeMut for Rtl8168 {
}
fn write(&mut self, _id: usize, buf: &[u8]) -> Result<usize> {
println!("Try Transmit {}", buf.len());
loop {
for (td_i, td) in self.transmit_ring.iter_mut().enumerate() {
if ! td.ctrl.readf(OWN) {
println!("Transmit {}: Setup {}", td_i, buf.len());
let mut data = &mut self.transmit_buffer[td_i as usize];
......@@ -129,21 +123,15 @@ impl SchemeMut for Rtl8168 {
i += 1;
}
println!("Transmit {}: Before: Control {:X}: Buffer {:X} TPPoll: {:X} ISR: {:X}", td_i, td.ctrl.read(), td.buffer.read(), self.regs.tppoll.read(), self.regs.isr.read());
let eor = td.ctrl.read() & EOR;
td.ctrl.write(OWN | eor | FS | LS | i as u32);
self.regs.tppoll.writef(1 << 6, true); //Notify of normal priority packet
println!("Transmit {}: During: Control {:X}: Buffer {:X} TPPoll: {:X} ISR: {:X}", td_i, td.ctrl.read(), td.buffer.read(), self.regs.tppoll.read(), self.regs.isr.read());
while self.regs.tppoll.readf(1 << 6) {
unsafe { asm!("pause" : : : "memory" : "intel", "volatile"); }
}
println!("Transmit {}: After: Control {:X}: Buffer {:X} TPPoll: {:X} ISR: {:X}", td_i, td.ctrl.read(), td.buffer.read(), self.regs.tppoll.read(), self.regs.isr.read());
return Ok(i);
}
}
......@@ -166,7 +154,7 @@ impl SchemeMut for Rtl8168 {
}
impl Rtl8168 {
pub unsafe fn new(base: usize, irq: u8) -> Result<Self> {
pub unsafe fn new(base: usize) -> Result<Self> {
assert_eq!(mem::size_of::<Regs>(), 256);
let regs = &mut *(base as *mut Regs);
......@@ -182,7 +170,6 @@ impl Rtl8168 {
let mut module = Rtl8168 {
regs: regs,
irq: irq,
receive_buffer: [Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?,
Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?,
Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?, Dma::zeroed()?,
......@@ -211,8 +198,6 @@ impl Rtl8168 {
}
pub unsafe fn init(&mut self) {
println!(" + RTL8168 on: {:X}, IRQ: {}", self.regs as *mut Regs as usize, self.irq);
let mac_low = self.regs.mac[0].read();
let mac_high = self.regs.mac[1].read();
let mac = [mac_low as u8,
......@@ -221,7 +206,7 @@ impl Rtl8168 {
(mac_low >> 24) as u8,
mac_high as u8,
(mac_high >> 8) as u8];
println!(" - MAC: {:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
print!("{}", format!(" - MAC: {:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]));
let _ = setcfg("mac", &format!("{:>02X}.{:>02X}.{:>02X}.{:>02X}.{:>02X}.{:>02X}", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]));
// Reset - this will disable tx and rx, reinitialize FIFOs, and set the system buffer pointer to the initial value
......@@ -294,18 +279,5 @@ impl Rtl8168 {
// Lock config
self.regs.cmd_9346.write(0);
println!(" - Ready CMD {:X} ISR {:X} IMR {:X} PHYS {:X} RMS {:X} MTPS {:X} RCR {:X} TCR {:X} RDSAR {:X} TNPDS {:X} THPDS {:X}",
self.regs.cmd.read(),
self.regs.isr.read(),
self.regs.imr.read(),
self.regs.phys_sts.read(),
self.regs.rms.read(),
self.regs.mtps.read(),
self.regs.rcr.read(),
self.regs.tcr.read(),
self.regs.rdsar[0].read(),
self.regs.tnpds[0].read(),
self.regs.thpds[0].read());
}
}
......@@ -28,6 +28,8 @@ fn main() {
let irq_str = args.next().expect("rtl8168d: no irq provided");
let irq = irq_str.parse::<u8>().expect("rtl8168d: failed to parse irq");
print!("{}", format!(" + RTL8168 on: {:X}, IRQ: {}", bar, irq));
thread::spawn(move || {
unsafe {
syscall::iopl(3).expect("rtl8168d: failed to get I/O permission");
......@@ -41,7 +43,7 @@ fn main() {
let address = unsafe { syscall::physmap(bar, 256, MAP_WRITE).expect("rtl8168d: failed to map address") };
{
let device = Arc::new(RefCell::new(unsafe { device::Rtl8168::new(address, irq).expect("rtl8168d: failed to allocate device") }));
let device = Arc::new(RefCell::new(unsafe { device::Rtl8168::new(address).expect("rtl8168d: failed to allocate device") }));
let mut event_queue = EventQueue::<usize>::new().expect("rtl8168d: failed to create event queue");
......@@ -56,8 +58,6 @@ fn main() {
let isr = unsafe { device_irq.borrow_mut().irq() };
if isr != 0 {
println!("RTL8168 ISR {:X}", isr);
irq_file.write(&mut irq)?;
let mut todo = todo_irq.borrow_mut();
......
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