From 5b8d53ddd38114874d3c361eb1f6e13496336110 Mon Sep 17 00:00:00 2001
From: 4lDO2 <4lDO2@protonmail.com>
Date: Thu, 27 Jun 2024 14:00:17 +0200
Subject: [PATCH] Fix x86_64 trampoline.
---
redox-rt/src/arch/x86_64.rs | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/redox-rt/src/arch/x86_64.rs b/redox-rt/src/arch/x86_64.rs
index 33d52167..b597928f 100644
--- a/redox-rt/src/arch/x86_64.rs
+++ b/redox-rt/src/arch/x86_64.rs
@@ -231,6 +231,7 @@ asmfunction!(__relibc_internal_sigentry: ["
push r13
push r14
push r15
+ sub rsp, 16
push rax // selected signal
@@ -258,7 +259,7 @@ asmfunction!(__relibc_internal_sigentry: ["
xrstor [rsp]
5:
- add rsp, 4096 + 32
+ add rsp, 4096 + 32 + 16
pop r15
pop r14
pop r13
@@ -277,8 +278,17 @@ asmfunction!(__relibc_internal_sigentry: ["
popfq
pop qword ptr fs:[{tcb_sa_off} + {sa_tmp_rip}]
+
+ // x86 lacks atomic instructions for setting both the stack and instruction pointer
+ // simultaneously, except the slow microcoded IRETQ instruction. Thus, we let the arch_pre
+ // function emulate atomicity between the pop rsp and indirect jump.
+
+ .globl __relibc_internal_sigentry_crit_first
__relibc_internal_sigentry_crit_first:
+
pop rsp
+
+ .globl __relibc_internal_sigentry_crit_second
__relibc_internal_sigentry_crit_second:
jmp qword ptr fs:[{tcb_sa_off} + {sa_tmp_rip}]
6:
--
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