Commit 10bba94b authored by Tamar Christina's avatar Tamar Christina

Fix the mask for the sqrdml(a|s)h instructions.

Rn is supposed to have a 5 bit range but instead was given 4 bits
causing these instructions to disassemble as unknown instructions.

opcodes/

	* aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.

gas/

	* testsuite/gas/aarch64/rdma.s: Test for larger register numbers.
	* testsuite/gas/aarch64/rdma.d: Update results.
	* testsuite/gas/aarch64/rdma-directive.d: Likewise.
parent 1e84581f
2018-04-25 Tamar Christina <tamar.christina@arm.com>
* testsuite/gas/aarch64/rdma.s: Test for larger register numbers.
* testsuite/gas/aarch64/rdma.d: Update results.
* testsuite/gas/aarch64/rdma-directive.d: Likewise.
2018-04-25 Nick Clifton <nickc@redhat.com>
* po/es.po: Updated Spanish translation.
......
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......@@ -24,8 +24,15 @@
.arch_extension rdma
.endif
.macro vect_inst I T
\I v0.\()\T, v1.\()\T, v2.\()\T
/* irp seems broken, so get creative. */
.macro vect_inst I, T
.irp x, 0.\T, 3.\T, 13.\T, 23.\T, 29.\T
.irp y, 1.\T, 4.\T, 14.\T, 24.\T, 30.\T
.irp z, 2.\T, 5.\T, 15.\T, 25.\T, 31.\T
\I v\x, v\y, v\z
.endr
.endr
.endr
.endm
.text
......@@ -45,9 +52,15 @@
scalar_inst \inst \reg
.endr
.endr
.macro vect_indexed_inst I S T N
\I v0.\S\T, v1.\S\T, v2.\T[\N]
.irp x, 0.\S\T, 3.\S\T, 13.\S\T, 23.\S\T, 29.\S\T
.irp y, 1.\S\T, 4.\S\T, 14.\S\T, 24.\S\T, 30.\S\T
.irp z, 0.\T[\N], 5.\T[\N], 10.\T[\N], 13.\T[\N], 15.\T[\N]
\I v\x, v\y, v\z
.endr
.endr
.endr
.endm
.text
......@@ -63,7 +76,7 @@
.endr
.endr
.endr
.macro scalar_indexed_inst I T N
\I \T\()0, \T\()1, v2.\T[\N]
.endm
......
2018-04-25 Tamar Christina <tamar.christina@arm.com>
* aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
......
......@@ -2601,8 +2601,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
SIMD_INSN ("bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
SIMD_INSN ("bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
/* AdvSIMD three same extension. */
RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
CNUM_INSN ("fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ),
CNUM_INSN ("fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ),
/* AdvSIMD shift by immediate. */
......
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