Commit 1f1e0a5d authored by Maciej W. Rozycki's avatar Maciej W. Rozycki

MIPS16/GAS/testsuite: Add cross-section R_MIPS16_PC16_S1 relocation tests

Add a pair of MIPS16 branch tests to verify correct R_MIPS16_PC16_S1
relocation generation for cross-section references in a single source.
This complements commit c9775dde ("MIPS16: Add R_MIPS16_PC16_S1
branch relocation support").

	gas/
	* testsuite/gas/mips/mips16-branch-reloc-4.d: New test.
	* testsuite/gas/mips/mips16-branch-reloc-5.d: New test.
	* testsuite/gas/mips/mips16-branch-reloc-4.s: New test source.
	* testsuite/gas/mips/mips16-branch-reloc-5.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
parent 75f31665
2018-02-20 Maciej W. Rozycki <macro@mips.com>
* testsuite/gas/mips/mips16-branch-reloc-4.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-5.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-4.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-5.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2018-02-20 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (struct litpool_frag): Add new field
......
......@@ -1750,6 +1750,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "mips16-branch-reloc-1"
run_dump_test "mips16-branch-reloc-2"
run_dump_test "mips16-branch-reloc-3"
run_dump_test "mips16-branch-reloc-4"
run_dump_test "mips16-branch-reloc-5"
run_dump_test "mips16-branch-addend-0"
run_dump_test "mips16-branch-addend-1"
run_dump_test "mips16-branch-addend-2"
......
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS16 branch relocation 4
#as: -32
.*: +file format .*mips.*
Disassembly of section \.text\.foo:
\.\.\.
[0-9a-f]+ <[^>]*> f7ff 101e b 00001000 <foo>
[ ]*[0-9a-f]+: R_MIPS16_PC16_S1 bar
[0-9a-f]+ <[^>]*> f7ff 601e bteqz 00001004 <foo\+0x4>
[ ]*[0-9a-f]+: R_MIPS16_PC16_S1 bar
[0-9a-f]+ <[^>]*> f7ff 611e btnez 00001008 <foo\+0x8>
[ ]*[0-9a-f]+: R_MIPS16_PC16_S1 bar
[0-9a-f]+ <[^>]*> f7ff 221e beqz v0,0000100c <foo\+0xc>
[ ]*[0-9a-f]+: R_MIPS16_PC16_S1 bar
[0-9a-f]+ <[^>]*> f7ff 2a1e bnez v0,00001010 <foo\+0x10>
[ ]*[0-9a-f]+: R_MIPS16_PC16_S1 bar
[0-9a-f]+ <[^>]*> 6500 nop
\.\.\.
Disassembly of section \.text\.bar:
[0-9a-f]+ <[^>]*> 6500 nop
\.\.\.
.section .text.foo, "ax", @progbits
.space 0x1000
.ent foo
.set mips16
foo:
b bar
bteqz bar
btnez bar
beqz $2, bar
bnez $2, bar
nop
.set nomips16
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.section .text.bar, "ax", @progbits
.ent bar
.set mips16
bar:
nop
.set nomips16
.end bar
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS16 branch relocation 5
#as: -32
.*: +file format .*mips.*
Disassembly of section \.text\.bar:
\.\.\.
[0-9a-f]+ <[^>]*> 6500 nop
\.\.\.
Disassembly of section \.text\.foo:
[0-9a-f]+ <[^>]*> f7ff 101e b 00000000 <foo>
[ ]*[0-9a-f]+: R_MIPS16_PC16_S1 bar
[0-9a-f]+ <[^>]*> f7ff 601e bteqz 00000004 <foo\+0x4>
[ ]*[0-9a-f]+: R_MIPS16_PC16_S1 bar
[0-9a-f]+ <[^>]*> f7ff 611e btnez 00000008 <foo\+0x8>
[ ]*[0-9a-f]+: R_MIPS16_PC16_S1 bar
[0-9a-f]+ <[^>]*> f7ff 221e beqz v0,0000000c <foo\+0xc>
[ ]*[0-9a-f]+: R_MIPS16_PC16_S1 bar
[0-9a-f]+ <[^>]*> f7ff 2a1e bnez v0,00000010 <foo\+0x10>
[ ]*[0-9a-f]+: R_MIPS16_PC16_S1 bar
[0-9a-f]+ <[^>]*> 6500 nop
\.\.\.
.section .text.bar, "ax", @progbits
.space 0x1000
.ent bar
.set mips16
bar:
nop
.set nomips16
.end bar
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.section .text.foo, "ax", @progbits
.ent foo
.set mips16
foo:
b bar
bteqz bar
btnez bar
beqz $2, bar
bnez $2, bar
nop
.set nomips16
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment