Commit 561a72d4 authored by Tamar Christina's avatar Tamar Christina

Modify AArch64 Assembly and disassembly functions to be able to fail and report why.

This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.

These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.

This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.

The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.

gas/

	PR binutils/21446
	* config/tc-aarch64.c (parse_sys_reg): Return register flags.
	(parse_operands): Fill in register flags.

gdb/

	PR binutils/21446
	* aarch64-tdep.c (aarch64_analyze_prologue,
	aarch64_software_single_step, aarch64_displaced_step_copy_insn):
	Indicate not interested in errors.

include/

	PR binutils/21446
	* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
	(aarch64_decode_insn): Accept error struct.

opcodes/

	PR binutils/21446
	* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
	and take error struct.
	* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
	aarch64_ins_reglist, aarch64_ins_ldst_reglist,
	aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
	aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
	aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
	aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
	aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
	aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
	aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
	aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
	aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
	aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
	aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
	aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
	aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
	aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
	aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
	aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
	aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
	aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
	aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
	aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
	aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
	aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
	* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
	* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
	aarch64_ext_reglist, aarch64_ext_ldst_reglist,
	aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
	aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
	aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
	aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
	aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
	aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
	aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
	aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
	aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
	aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
	aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
	aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
	aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
	aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
	aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
	aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
	aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
	aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
	aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
	aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
	aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
	aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
	(determine_disassembling_preference, aarch64_decode_insn,
	print_insn_aarch64_word, print_insn_data): Take errors struct.
	(print_insn_aarch64): Use errors.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-gen.c (print_operand_inserter): Use errors and change type to
	boolean in aarch64_insert_operan.
	(print_operand_extractor): Likewise.
	* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
parent 4e6ff0e1
2018-05-15 Tamar Christina <tamar.christina@arm.com>
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
2018-05-14 Nick Clifton <nickc@redhat.com>
* write.c (maybe_generate_build_notes): Generate notes on a
......
......@@ -3934,7 +3934,8 @@ parse_barrier_psb (char **str,
static int
parse_sys_reg (char **str, struct hash_control *sys_regs,
int imple_defined_p, int pstatefield_p)
int imple_defined_p, int pstatefield_p,
uint32_t* flags)
{
char *p, *q;
char buf[32];
......@@ -3965,6 +3966,8 @@ parse_sys_reg (char **str, struct hash_control *sys_regs,
if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
return PARSE_FAIL;
value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
if (flags)
*flags = 0;
}
}
else
......@@ -3979,6 +3982,8 @@ parse_sys_reg (char **str, struct hash_control *sys_regs,
as_warn (_("system register name '%s' is deprecated and may be "
"removed in a future release"), buf);
value = o->value;
if (flags)
*flags = o->flags;
}
*str = q;
......@@ -6347,17 +6352,21 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto regoff_addr;
case AARCH64_OPND_SYSREG:
if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0))
== PARSE_FAIL)
{
set_syntax_error (_("unknown or missing system register name"));
goto failure;
}
inst.base.operands[i].sysreg = val;
break;
{
uint32_t sysreg_flags;
if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0,
&sysreg_flags)) == PARSE_FAIL)
{
set_syntax_error (_("unknown or missing system register name"));
goto failure;
}
inst.base.operands[i].sysreg.value = val;
inst.base.operands[i].sysreg.flags = sysreg_flags;
break;
}
case AARCH64_OPND_PSTATEFIELD:
if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1))
if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1, NULL))
== PARSE_FAIL)
{
set_syntax_error (_("unknown or missing PSTATE field name"));
......
2018-05-15 Tamar Christina <tamar.christina@arm.com>
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
2018-05-15 Maciej W. Rozycki <macro@mips.com>
* mips-linux-nat.c (mips_linux_nat_target::fetch_registers):
......
......@@ -244,7 +244,7 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
insn = reader.read (start, 4, byte_order_for_code);
if (aarch64_decode_insn (insn, &inst, 1) != 0)
if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
break;
if (inst.opcode->iclass == addsub_imm
......@@ -2425,7 +2425,7 @@ aarch64_software_single_step (struct regcache *regcache)
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
aarch64_inst inst;
if (aarch64_decode_insn (insn, &inst, 1) != 0)
if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
return {};
/* Look for a Load Exclusive instruction which begins the sequence. */
......@@ -2438,7 +2438,7 @@ aarch64_software_single_step (struct regcache *regcache)
insn = read_memory_unsigned_integer (loc, insn_size,
byte_order_for_code);
if (aarch64_decode_insn (insn, &inst, 1) != 0)
if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
return {};
/* Check if the instruction is a conditional branch. */
if (inst.opcode->iclass == condbranch)
......@@ -2731,7 +2731,7 @@ aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
struct aarch64_displaced_step_data dsd;
aarch64_inst inst;
if (aarch64_decode_insn (insn, &inst, 1) != 0)
if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
return NULL;
/* Look for a Load Exclusive instruction which begins the sequence. */
......
2018-05-15 Tamar Christina <tamar.christina@arm.com>
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
2018-05-15 Francois H. Theron <francois.theron@netronome.com>
* opcode/nfp.h: Use uint64_t instead of bfd_vma.
......
......@@ -957,9 +957,17 @@ struct aarch64_opnd_info
unsigned preind : 1; /* Pre-indexed. */
unsigned postind : 1; /* Post-indexed. */
} addr;
struct
{
/* The encoding of the system register. */
aarch64_insn value;
/* The system register flags. */
uint32_t flags;
} sysreg;
const aarch64_cond *cond;
/* The encoding of the system register. */
aarch64_insn sysreg;
/* The encoding of the PSTATE field. */
aarch64_insn pstatefield;
const aarch64_sys_ins_reg *sysins_op;
......@@ -1138,7 +1146,8 @@ extern int
aarch64_zero_register_p (const aarch64_opnd_info *);
extern int
aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
aarch64_operand_error *errors);
/* Given an operand qualifier, return the expected data element size
of a qualified operand. */
......
2018-05-15 Tamar Christina <tamar.christina@arm.com>
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 Francois H. Theron <francois.theron@netronome.com>
* nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
......
......@@ -579,10 +579,11 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
return aarch64_opcode_table + value;
}
const char*
bfd_boolean
aarch64_insert_operand (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code, const aarch64_inst *inst)
aarch64_insn *code, const aarch64_inst *inst,
aarch64_operand_error *errors)
{
/* Use the index as the key. */
int key = self - aarch64_operands;
......@@ -634,26 +635,26 @@ aarch64_insert_operand (const aarch64_operand *self,
case 182:
case 186:
case 189:
return aarch64_ins_regno (self, info, code, inst);
return aarch64_ins_regno (self, info, code, inst, errors);
case 13:
return aarch64_ins_reg_extended (self, info, code, inst);
return aarch64_ins_reg_extended (self, info, code, inst, errors);
case 14:
return aarch64_ins_reg_shifted (self, info, code, inst);
return aarch64_ins_reg_shifted (self, info, code, inst, errors);
case 19:
return aarch64_ins_ft (self, info, code, inst);
return aarch64_ins_ft (self, info, code, inst, errors);
case 30:
case 31:
case 32:
case 191:
return aarch64_ins_reglane (self, info, code, inst);
return aarch64_ins_reglane (self, info, code, inst, errors);
case 33:
return aarch64_ins_reglist (self, info, code, inst);
return aarch64_ins_reglist (self, info, code, inst, errors);
case 34:
return aarch64_ins_ldst_reglist (self, info, code, inst);
return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
case 35:
return aarch64_ins_ldst_reglist_r (self, info, code, inst);
return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
case 36:
return aarch64_ins_ldst_elemlist (self, info, code, inst);
return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
case 37:
case 38:
case 39:
......@@ -686,85 +687,85 @@ aarch64_insert_operand (const aarch64_operand *self,
case 171:
case 172:
case 173:
return aarch64_ins_imm (self, info, code, inst);
return aarch64_ins_imm (self, info, code, inst, errors);
case 41:
case 42:
return aarch64_ins_advsimd_imm_shift (self, info, code, inst);
return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
case 43:
case 44:
case 45:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 49:
case 140:
return aarch64_ins_fpimm (self, info, code, inst);
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 64:
case 147:
return aarch64_ins_limm (self, info, code, inst);
return aarch64_ins_limm (self, info, code, inst, errors);
case 65:
return aarch64_ins_aimm (self, info, code, inst);
return aarch64_ins_aimm (self, info, code, inst, errors);
case 66:
return aarch64_ins_imm_half (self, info, code, inst);
return aarch64_ins_imm_half (self, info, code, inst, errors);
case 67:
return aarch64_ins_fbits (self, info, code, inst);
return aarch64_ins_fbits (self, info, code, inst, errors);
case 69:
case 70:
case 145:
return aarch64_ins_imm_rotate2 (self, info, code, inst);
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 71:
case 144:
return aarch64_ins_imm_rotate1 (self, info, code, inst);
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 72:
case 73:
return aarch64_ins_cond (self, info, code, inst);
return aarch64_ins_cond (self, info, code, inst, errors);
case 79:
case 86:
return aarch64_ins_addr_simple (self, info, code, inst);
return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 80:
return aarch64_ins_addr_regoff (self, info, code, inst);
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
case 81:
case 82:
case 83:
return aarch64_ins_addr_simm (self, info, code, inst);
return aarch64_ins_addr_simm (self, info, code, inst, errors);
case 84:
return aarch64_ins_addr_simm10 (self, info, code, inst);
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
case 85:
return aarch64_ins_addr_uimm12 (self, info, code, inst);
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
case 87:
return aarch64_ins_addr_offset (self, info, code, inst);
return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 88:
return aarch64_ins_simd_addr_post (self, info, code, inst);
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
case 89:
return aarch64_ins_sysreg (self, info, code, inst);
return aarch64_ins_sysreg (self, info, code, inst, errors);
case 90:
return aarch64_ins_pstatefield (self, info, code, inst);
return aarch64_ins_pstatefield (self, info, code, inst, errors);
case 91:
case 92:
case 93:
case 94:
return aarch64_ins_sysins_op (self, info, code, inst);
return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 95:
case 96:
return aarch64_ins_barrier (self, info, code, inst);
return aarch64_ins_barrier (self, info, code, inst, errors);
case 97:
return aarch64_ins_prfop (self, info, code, inst);
return aarch64_ins_prfop (self, info, code, inst, errors);
case 98:
return aarch64_ins_hint (self, info, code, inst);
return aarch64_ins_hint (self, info, code, inst, errors);
case 99:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst);
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 100:
case 101:
case 102:
case 103:
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 104:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 105:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 106:
case 107:
case 108:
case 109:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 110:
case 111:
case 112:
......@@ -778,7 +779,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 120:
case 121:
case 122:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 123:
case 124:
case 125:
......@@ -787,49 +788,49 @@ aarch64_insert_operand (const aarch64_operand *self,
case 128:
case 129:
case 130:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 131:
case 132:
case 133:
case 134:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 135:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 136:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 137:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 138:
return aarch64_ins_sve_aimm (self, info, code, inst);
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
case 139:
return aarch64_ins_sve_asimm (self, info, code, inst);
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
case 141:
return aarch64_ins_sve_float_half_one (self, info, code, inst);
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 142:
return aarch64_ins_sve_float_half_two (self, info, code, inst);
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
case 143:
return aarch64_ins_sve_float_zero_one (self, info, code, inst);
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
case 146:
return aarch64_ins_inv_limm (self, info, code, inst);
return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 148:
return aarch64_ins_sve_limm_mov (self, info, code, inst);
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
case 150:
return aarch64_ins_sve_scale (self, info, code, inst);
return aarch64_ins_sve_scale (self, info, code, inst, errors);
case 162:
case 163:
return aarch64_ins_sve_shlimm (self, info, code, inst);
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 164:
case 165:
return aarch64_ins_sve_shrimm (self, info, code, inst);
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 183:
case 184:
case 185:
return aarch64_ins_sve_quad_index (self, info, code, inst);
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 187:
return aarch64_ins_sve_index (self, info, code, inst);
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 188:
case 190:
return aarch64_ins_sve_reglist (self, info, code, inst);
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
}
This diff is collapsed.
......@@ -30,15 +30,17 @@ const aarch64_opcode* aarch64_find_real_opcode (const aarch64_opcode *);
/* Switch-table-based high-level operand inserter. */
const char* aarch64_insert_operand (const aarch64_operand *,
bfd_boolean aarch64_insert_operand (const aarch64_operand *,
const aarch64_opnd_info *, aarch64_insn *,
const aarch64_inst *);
const aarch64_inst *,
aarch64_operand_error *);
/* Operand inserters. */
#define AARCH64_DECL_OPD_INSERTER(x) \
const char* aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
aarch64_insn *, const aarch64_inst *)
bfd_boolean aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
aarch64_insn *, const aarch64_inst *, \
aarch64_operand_error *)
AARCH64_DECL_OPD_INSERTER (ins_regno);
AARCH64_DECL_OPD_INSERTER (ins_reglane);
......
......@@ -19688,10 +19688,11 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)
return aarch64_opcode_table + value;
}
int
bfd_boolean
aarch64_extract_operand (const aarch64_operand *self,
aarch64_opnd_info *info,
aarch64_insn code, const aarch64_inst *inst)
aarch64_insn code, const aarch64_inst *inst,
aarch64_operand_error *errors)
{
/* Use the index as the key. */
int key = self - aarch64_operands;
......@@ -19742,30 +19743,30 @@ aarch64_extract_operand (const aarch64_operand *self,
case 182:
case 186:
case 189:
return aarch64_ext_regno (self, info, code, inst);
return aarch64_ext_regno (self, info, code, inst, errors);
case 8:
return aarch64_ext_regrt_sysins (self, info, code, inst);
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
case 12:
return aarch64_ext_regno_pair (self, info, code, inst);
return aarch64_ext_regno_pair (self, info, code, inst, errors);
case 13:
return aarch64_ext_reg_extended (self, info, code, inst);
return aarch64_ext_reg_extended (self, info, code, inst, errors);
case 14:
return aarch64_ext_reg_shifted (self, info, code, inst);
return aarch64_ext_reg_shifted (self, info, code, inst, errors);
case 19:
return aarch64_ext_ft (self, info, code, inst);
return aarch64_ext_ft (self, info, code, inst, errors);
case 30:
case 31:
case 32:
case 191:
return aarch64_ext_reglane (self, info, code, inst);
return aarch64_ext_reglane (self, info, code, inst, errors);
case 33:
return aarch64_ext_reglist (self, info, code, inst);
return aarch64_ext_reglist (self, info, code, inst, errors);
case 34:
return aarch64_ext_ldst_reglist (self, info, code, inst);
return aarch64_ext_ldst_reglist (self, info, code, inst, errors);
case 35:
return aarch64_ext_ldst_reglist_r (self, info, code, inst);
return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors);
case 36:
return aarch64_ext_ldst_elemlist (self, info, code, inst);
return aarch64_ext_ldst_elemlist (self, info, code, inst, errors);
case 37:
case 38:
case 39:
......@@ -19799,87 +19800,87 @@ aarch64_extract_operand (const aarch64_operand *self,
case 171:
case 172:
case 173:
return aarch64_ext_imm (self, info, code, inst);
return aarch64_ext_imm (self, info, code, inst, errors);
case 41:
case 42:
return aarch64_ext_advsimd_imm_shift (self, info, code, inst);
return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors);
case 43:
case 44:
case 45:
return aarch64_ext_advsimd_imm_modified (self, info, code, inst);
return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors);
case 46:
return aarch64_ext_shll_imm (self, info, code, inst);
return aarch64_ext_shll_imm (self, info, code, inst, errors);
case 49:
case 140:
return aarch64_ext_fpimm (self, info, code, inst);
return aarch64_ext_fpimm (self, info, code, inst, errors);
case 64:
case 147:
return aarch64_ext_limm (self, info, code, inst);
return aarch64_ext_limm (self, info, code, inst, errors);
case 65:
return aarch64_ext_aimm (self, info, code, inst);
return aarch64_ext_aimm (self, info, code, inst, errors);
case 66:
return aarch64_ext_imm_half (self, info, code, inst);
return aarch64_ext_imm_half (self, info, code, inst, errors);
case 67:
return aarch64_ext_fbits (self, info, code, inst);
return aarch64_ext_fbits (self, info, code, inst, errors);
case 69:
case 70:
case 145:
return aarch64_ext_imm_rotate2 (self, info, code, inst);
return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
case 71:
case 144:
return aarch64_ext_imm_rotate1 (self, info, code, inst);
return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
case 72:
case 73:
return aarch64_ext_cond (self, info, code, inst);
return aarch64_ext_cond (self, info, code, inst, errors);
case 79:
case 86:
return aarch64_ext_addr_simple (self, info, code, inst);
return aarch64_ext_addr_simple (self, info, code, inst, errors);
case 80:
return aarch64_ext_addr_regoff (self, info, code, inst);
return aarch64_ext_addr_regoff (self, info, code, inst, errors);
case 81:
case 82:
case 83:
return aarch64_ext_addr_simm (self, info, code, inst);
return aarch64_ext_addr_simm (self, info, code, inst, errors);
case 84:
return aarch64_ext_addr_simm10 (self, info, code, inst);
return aarch64_ext_addr_simm10 (self, info, code, inst, errors);
case 85:
return aarch64_ext_addr_uimm12 (self, info, code, inst);
return aarch64_ext_addr_uimm12 (self, info, code, inst, errors);
case 87:
return aarch64_ext_addr_offset (self, info, code, inst);
return aarch64_ext_addr_offset (self, info, code, inst, errors);
case 88:
return aarch64_ext_simd_addr_post (self, info, code, inst);
return aarch64_ext_simd_addr_post (self, info, code, inst, errors);
case 89:
return aarch64_ext_sysreg (self, info, code, inst);
return aarch64_ext_sysreg (self, info, code, inst, errors);
case 90:
return aarch64_ext_pstatefield (self, info, code, inst);
return aarch64_ext_pstatefield (self, info, code, inst, errors);
case 91:
case 92:
case 93:
case 94:
return aarch64_ext_sysins_op (self, info, code, inst);
return aarch64_ext_sysins_op (self, info, code, inst, errors);
case 95:
case 96:
return aarch64_ext_barrier (self, info, code, inst);
return aarch64_ext_barrier (self, info, code, inst, errors);
case 97:
return aarch64_ext_prfop (self, info, code, inst);