Commit 730c3174 authored by Scott Egerton's avatar Scott Egerton Committed by Maciej W. Rozycki

MIPS: Add CRC ASE support

Add support for the CRC Application Specific Extension for Release 6 of
the MIPS Architecture.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
    Instruction Set Manual", Imagination Technologies Ltd., Document
    Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
    "Alphabetical List of Instructions", pp. 143-148

[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
    Instruction Set Manual", Imagination Technologies Ltd., Document
    Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
    "Alphabetical List of Instructions", pp. 165-170

ChangeLog:

bfd/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* elfxx-mips.c (print_mips_ases): Add CRC.

binutils/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* readelf.c (print_mips_ases): Add CRC.

gas/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
            Maciej W. Rozycki  <macro@mips.com>

	* config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
	(md_longopts): Likewise.
	(md_show_usage): Add help for -mcrc and -mno-crc.
	(mips_ases): Define availability for CRC and CRC64.
	(mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
	* doc/as.texinfo: Document -mcrc, -mno-crc.
	* doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
	.set no-crc.
	* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
	ASE.
	* testsuite/gas/mips/ase-errors-2.l: Likewise.
	* testsuite/gas/mips/ase-errors-1.s: Likewise.
	* testsuite/gas/mips/ase-errors-2.s: Likewise.
	* testsuite/gas/mips/crc.d: New test.
	* testsuite/gas/mips/crc64.d: New test.
	* testsuite/gas/mips/crc-err.d: New test.
	* testsuite/gas/mips/crc64-err.d: New test.
	* testsuite/gas/mips/crc-err.l: New test stderr output.
	* testsuite/gas/mips/crc64-err.l: New test stderr output.
	* testsuite/gas/mips/crc.s: New test source.
	* testsuite/gas/mips/crc64.s: New test source.
	* testsuite/gas/mips/crc-err.s: New test source.
	* testsuite/gas/mips/crc64-err.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

include/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* elf/mips.h (AFL_ASE_CRC): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
	* opcode/mips.h (ASE_CRC): New macro.
	* opcode/mips.h (ASE_CRC64): Likewise.

opcodes/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
	* mips-opc.c (CRC, CRC64): New macros.
	(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
	crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
	crc32cd for CRC64.
parent a08ac84b
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elfxx-mips.c (print_mips_ases): Add CRC.
2018-06-08 H.J. Lu <hongjiu.lu@intel.com>
PR ld/23161
......
......@@ -15641,6 +15641,8 @@ print_mips_ases (FILE *file, unsigned int mask)
fputs ("\n\tXPA ASE", file);
if (mask & AFL_ASE_MIPS16E2)
fputs ("\n\tMIPS16e2 ASE", file);
if (mask & AFL_ASE_CRC)
fputs ("\n\tCRC ASE", file);
if (mask == 0)
fprintf (file, "\n\t%s", _("None"));
else if ((mask & ~AFL_ASE_MASK) != 0)
......
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* readelf.c (print_mips_ases): Add CRC.
2018-06-13 Nick Clifton <nickc@redhat.com>
* doc/binutils.texi (objdump): Add missing closing square
......
......@@ -15504,6 +15504,8 @@ print_mips_ases (unsigned int mask)
fputs ("\n\tXPA ASE", stdout);
if (mask & AFL_ASE_MIPS16E2)
fputs ("\n\tMIPS16e2 ASE", stdout);
if (mask & AFL_ASE_CRC)
fputs ("\n\tCRC ASE", stdout);
if (mask == 0)
fprintf (stdout, "\n\t%s", _("None"));
else if ((mask & ~AFL_ASE_MASK) != 0)
......
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
(md_longopts): Likewise.
(md_show_usage): Add help for -mcrc and -mno-crc.
(mips_ases): Define availability for CRC and CRC64.
(mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
* doc/as.texinfo: Document -mcrc, -mno-crc.
* doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
.set no-crc.
* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
ASE.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ase-errors-1.s: Likewise.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/crc.d: New test.
* testsuite/gas/mips/crc64.d: New test.
* testsuite/gas/mips/crc-err.d: New test.
* testsuite/gas/mips/crc64-err.d: New test.
* testsuite/gas/mips/crc-err.l: New test stderr output.
* testsuite/gas/mips/crc64-err.l: New test stderr output.
* testsuite/gas/mips/crc.s: New test source.
* testsuite/gas/mips/crc64.s: New test source.
* testsuite/gas/mips/crc-err.s: New test source.
* testsuite/gas/mips/crc64-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2018-06-11 Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (md_show_usage): Correct help text for `-O0'
......
-*- text -*-
* Add support for the MIPS Cyclic Redudancy Check (CRC) ASE.
* Add support for the Freescale S12Z architecture.
* Add --generate-missing-build-notes=[yes|no] option to create (or not) GNU
......
......@@ -1460,6 +1460,8 @@ enum options
OPTION_NO_MCU,
OPTION_MIPS16E2,
OPTION_NO_MIPS16E2,
OPTION_CRC,
OPTION_NO_CRC,
OPTION_M4650,
OPTION_NO_M4650,
OPTION_M4010,
......@@ -1581,6 +1583,8 @@ struct option md_longopts[] =
{"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
{"mmips16e2", no_argument, NULL, OPTION_MIPS16E2},
{"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2},
{"mcrc", no_argument, NULL, OPTION_CRC},
{"mno-crc", no_argument, NULL, OPTION_NO_CRC},
/* Old-style architecture options. Don't add more of these. */
{"m4650", no_argument, NULL, OPTION_M4650},
......@@ -1768,6 +1772,11 @@ static const struct mips_ase mips_ases[] = {
OPTION_MIPS16E2, OPTION_NO_MIPS16E2,
2, 2, -1, -1,
6 },
{ "crc", ASE_CRC, ASE_CRC64,
OPTION_CRC, OPTION_NO_CRC,
6, 6, -1, -1,
-1 },
};
/* The set of ASEs that require -mfp64. */
......@@ -18976,6 +18985,8 @@ mips_convert_ase_flags (int ase)
ext_ases |= AFL_ASE_XPA;
if (ase & ASE_MIPS16E2)
ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0;
if (ase & ASE_CRC)
ext_ases |= AFL_ASE_CRC;
return ext_ases;
}
......@@ -19990,6 +20001,9 @@ MIPS options:\n\
-mvirt generate Virtualization instructions\n\
-mno-virt do not generate Virtualization instructions\n"));
fprintf (stream, _("\
-mcrc generate CRC instructions\n\
-mno-crc do not generate CRC instructions\n"));
fprintf (stream, _("\
-minsn32 only generate 32-bit microMIPS instructions\n\
-mno-insn32 generate all microMIPS instructions\n"));
fprintf (stream, _("\
......
......@@ -422,6 +422,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-mxpa}] [@b{-mno-xpa}]
[@b{-mmt}] [@b{-mno-mt}]
[@b{-mmcu}] [@b{-mno-mcu}]
[@b{-mcrc}] [@b{-mno-crc}]
[@b{-minsn32}] [@b{-mno-insn32}]
[@b{-mfix7000}] [@b{-mno-fix7000}]
[@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
......@@ -1512,6 +1513,12 @@ Generate code for the MCU Application Specific Extension.
This tells the assembler to accept MCU instructions.
@samp{-mno-mcu} turns off this option.
@item -mcrc
@itemx -mno-crc
Generate code for the MIPS cyclic redundancy check (CRC) Application
Specific Extension. This tells the assembler to accept CRC instructions.
@samp{-mno-crc} turns off this option.
@item -minsn32
@itemx -mno-insn32
Only use 32-bit instruction encodings when generating code for the
......
......@@ -234,6 +234,12 @@ Generate code for the Virtualization Application Specific Extension.
This tells the assembler to accept Virtualization instructions.
@samp{-mno-virt} turns off this option.
@item -mcrc
@itemx -mno-crc
Generate code for the cyclic redundancy check (CRC) Application Specific
Extension. This tells the assembler to accept CRC instructions.
@samp{-mno-crc} turns off this option.
@item -minsn32
@itemx -mno-insn32
Only use 32-bit instruction encodings when generating code for the
......@@ -1111,6 +1117,13 @@ prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. Neither
directive affects the state of MIPS16 mode being active itself which has
separate controls.
@cindex MIPS cyclic redundancy check (CRC) instruction generation override
@kindex @code{.set crc}
@kindex @code{.set nocrc}
The directive @code{.set crc} makes the assembler accept instructions
from the CRC Extension from that point on in the assembly. The
@code{.set nocrc} directive prevents CRC instructions from being accepted.
Traditional MIPS assemblers do not support these directives.
@node MIPS Floating-Point
......
......@@ -40,3 +40,7 @@
# ----------------------------------------------------------------------------
.*:100: Warning: the `eva' extension requires MIPS32 revision 2 or greater
.*:103: Error: opcode not supported.* `lbue \$4,16\(\$5\)'
# ----------------------------------------------------------------------------
.*:108: Error: opcode not supported.* `crc32d \$4,\$7,\$4'
.*:109: Warning: the `crc' extension requires MIPS32 revision 6 or greater
.*:112: Error: opcode not supported.* `crc32b \$4,\$7,\$4'
......@@ -102,6 +102,15 @@
.set noeva
lbue $4,16($5) # ERROR: eva not enabled
.set mips32r6
.set crc # OK
crc32b $4,$7,$4 # OK
crc32d $4,$7,$4 # ERROR: 64-bit only
.set mips32r5 # ERROR: too low
crc32b $4,$7,$4 # OK
.set nocrc
crc32b $4,$7,$4 # ERROR: crc not enabled
# There should be no errors after this.
.set fp=32
.set mips1
......
......@@ -32,3 +32,7 @@
# ----------------------------------------------------------------------------
.*:84: Warning: the `eva' extension requires MIPS64 revision 2 or greater
.*:87: Error: opcode not supported.* `lbue \$4,16\(\$5\)'
# ----------------------------------------------------------------------------
.*:93: Warning: the `crc' extension requires MIPS64 revision 6 or greater
.*:97: Error: opcode not supported.* `crc32b \$4,\$7,\$4'
.*:98: Error: opcode not supported.* `crc32d \$4,\$7,\$4'
......@@ -86,6 +86,17 @@
.set noeva
lbue $4,16($5) # ERROR: eva not enabled
.set mips64r6
.set crc # OK
crc32b $4,$7,$4 # OK
crc32d $4,$7,$4 # OK
.set mips64r5 # ERROR: too low
crc32b $4,$7,$4 # OK
crc32d $4,$7,$4 # OK
.set nocrc
crc32b $4,$7,$4 # ERROR: crc not enabled
crc32d $4,$7,$4 # ERROR: crc not enabled
# There should be no errors after this.
.set fp=32
.set mips4
......
#name: MIPS CRC instruction errors
#as: -32 -mcrc
#error-output: crc-err.l
.*: Assembler messages:
.*:4: Error: invalid operands `crc32b \$5,\$4,\$4'
.*:6: Error: invalid operands `crc32b \$4,\$4,\$5'
.*:7: Error: invalid operands `crc32b \$4,\$5,\$6'
.*:9: Error: invalid operands `crc32h \$5,\$4,\$4'
.*:11: Error: invalid operands `crc32h \$4,\$4,\$5'
.*:12: Error: invalid operands `crc32h \$4,\$5,\$6'
.*:14: Error: invalid operands `crc32w \$5,\$4,\$4'
.*:16: Error: invalid operands `crc32w \$4,\$4,\$5'
.*:17: Error: invalid operands `crc32w \$4,\$5,\$6'
.*:19: Error: invalid operands `crc32cb \$5,\$4,\$4'
.*:21: Error: invalid operands `crc32cb \$4,\$4,\$5'
.*:22: Error: invalid operands `crc32cb \$4,\$5,\$6'
.*:24: Error: invalid operands `crc32ch \$5,\$4,\$4'
.*:26: Error: invalid operands `crc32ch \$4,\$4,\$5'
.*:27: Error: invalid operands `crc32ch \$4,\$5,\$6'
.*:29: Error: invalid operands `crc32cw \$5,\$4,\$4'
.*:31: Error: invalid operands `crc32cw \$4,\$4,\$5'
.*:32: Error: invalid operands `crc32cw \$4,\$5,\$6'
.text
test_crc:
crc32b $4,$4,$4
crc32b $5,$4,$4
crc32b $4,$5,$4
crc32b $4,$4,$5
crc32b $4,$5,$6
crc32h $4,$4,$4
crc32h $5,$4,$4
crc32h $4,$5,$4
crc32h $4,$4,$5
crc32h $4,$5,$6
crc32w $4,$4,$4
crc32w $5,$4,$4
crc32w $4,$5,$4
crc32w $4,$4,$5
crc32w $4,$5,$6
crc32cb $4,$4,$4
crc32cb $5,$4,$4
crc32cb $4,$5,$4
crc32cb $4,$4,$5
crc32cb $4,$5,$6
crc32ch $4,$4,$4
crc32ch $5,$4,$4
crc32ch $4,$5,$4
crc32ch $4,$4,$5
crc32ch $4,$5,$6
crc32cw $4,$4,$4
crc32cw $5,$4,$4
crc32cw $4,$5,$4
crc32cw $4,$4,$5
crc32cw $4,$5,$6
#objdump: -pdr --prefix-addresses --show-raw-insn
#name: MIPS CRC
#as: -mcrc -32
# Test the CRC instructions
.*: +file format .*mips.*
#...
ASEs:
#...
CRC ASE
#...
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 7ce4000f crc32b a0,a3,a0
[0-9a-f]+ <[^>]*> 7ce4004f crc32h a0,a3,a0
[0-9a-f]+ <[^>]*> 7ce4008f crc32w a0,a3,a0
[0-9a-f]+ <[^>]*> 7ce4010f crc32cb a0,a3,a0
[0-9a-f]+ <[^>]*> 7ce4014f crc32ch a0,a3,a0
[0-9a-f]+ <[^>]*> 7ce4018f crc32cw a0,a3,a0
\.\.\.
.text
test_crc:
crc32b $4,$7,$4
crc32h $4,$7,$4
crc32w $4,$7,$4
crc32cb $4,$7,$4
crc32ch $4,$7,$4
crc32cw $4,$7,$4
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
#name: MIPS CRC64 instruction errors
#as: -mcrc
#error-output: crc64-err.l
.*: Assembler messages:
.*:4: Error: invalid operands `crc32d \$5,\$4,\$4'
.*:6: Error: invalid operands `crc32d \$4,\$4,\$5'
.*:7: Error: invalid operands `crc32d \$4,\$5,\$6'
.*:9: Error: invalid operands `crc32cd \$5,\$4,\$4'
.*:11: Error: invalid operands `crc32cd \$4,\$4,\$5'
.*:12: Error: invalid operands `crc32cd \$4,\$5,\$6'
.text
test_crc:
crc32d $4,$4,$4
crc32d $5,$4,$4
crc32d $4,$5,$4
crc32d $4,$4,$5
crc32d $4,$5,$6
crc32cd $4,$4,$4
crc32cd $5,$4,$4
crc32cd $4,$5,$4
crc32cd $4,$4,$5
crc32cd $4,$5,$6
#objdump: -pdr --prefix-addresses --show-raw-insn
#name: MIPS CRC64
#as: -mcrc
# Test the CRC64 instructions
.*: +file format .*mips.*
#...
ASEs:
#...
CRC ASE
#...
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 7ce400cf crc32d a0,a3,a0
[0-9a-f]+ <[^>]*> 7ce401cf crc32cd a0,a3,a0
\.\.\.
.text
test_crc:
crc32d $4,$7,$4
crc32cd $4,$7,$4
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
......@@ -2056,4 +2056,9 @@ if { [istarget mips*-*-vxworks*] } {
run_list_test_arches "r6-branch-constraints" "-32" \
[mips_arch_list_matching mips32r6]
run_dump_test_arches "crc" [mips_arch_list_matching mips32r6]
run_dump_test_arches "crc-err" [mips_arch_list_matching mips32r6]
run_dump_test_arches "crc64" [mips_arch_list_matching mips64r6]
run_dump_test_arches "crc64-err" [mips_arch_list_matching mips64r6]
}
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elf/mips.h (AFL_ASE_CRC): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
* opcode/mips.h (ASE_CRC): New macro.
* opcode/mips.h (ASE_CRC64): Likewise.
2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
* elf/xtensa.h (xtensa_read_table_entries)
......
......@@ -1235,7 +1235,8 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
#define AFL_ASE_XPA 0x00001000 /* XPA ASE. */
#define AFL_ASE_DSPR3 0x00002000 /* DSP R3 ASE. */
#define AFL_ASE_MIPS16E2 0x00004000 /* MIPS16e2 ASE. */
#define AFL_ASE_MASK 0x00007fff /* All ASEs. */
#define AFL_ASE_CRC 0x00008000 /* CRC ASE. */
#define AFL_ASE_MASK 0x0000ffff /* All ASEs. */
/* Values for the isa_ext word of an ABI flags structure. */
......
......@@ -1294,6 +1294,9 @@ static const unsigned int mips_isa_table[] = {
/* The Virtualization ASE has eXtended Physical Addressing (XPA)
instructions which are only valid when both ASEs are enabled. */
#define ASE_XPA_VIRT 0x00020000
/* Cyclic redundancy check (CRC) ASE. */
#define ASE_CRC 0x00040000
#define ASE_CRC64 0x00080000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
......
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
* mips-opc.c (CRC, CRC64): New macros.
(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
crc32cd for CRC64.
2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
PR 20319
......
......@@ -563,7 +563,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
ISA_MIPS32R6,
(ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
| ASE_DSPR2 | ASE_DSPR3),
| ASE_DSPR2 | ASE_DSPR3 | ASE_CRC),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
......@@ -602,7 +602,8 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6,
ISA_MIPS64R6,
(ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
| ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3),
| ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC
| ASE_CRC64),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
......
......@@ -404,6 +404,10 @@ decode_mips_operand (const char *p)
#define XPA ASE_XPA
#define XPAVZ ASE_XPA_VIRT
/* Cyclic redundancy check instruction (CRC) support. */
#define CRC ASE_CRC
#define CRC64 ASE_CRC64
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
......@@ -3347,6 +3351,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"aluipc", "s,u", 0xec1f0000, 0xfc1f0000, WR_1, RD_pc, I37, 0, 0 },
/* MIPS cyclic redundancy check (CRC) ASE. */
{"crc32b", "t,s,-d", 0x7c00000f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 },
{"crc32h", "t,s,-d", 0x7c00004f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 },
{"crc32w", "t,s,-d", 0x7c00008f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 },
{"crc32d", "t,s,-d", 0x7c0000cf, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC64, 0 },
{"crc32cb", "t,s,-d", 0x7c00010f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 },
{"crc32ch", "t,s,-d", 0x7c00014f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 },
{"crc32cw", "t,s,-d", 0x7c00018f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 },
{"crc32cd", "t,s,-d", 0x7c0001cf, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC64, 0 },
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
......
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