Commit ae1d3843 authored by H.J. Lu's avatar H.J. Lu

x86: Allow 32-bit registers for tpause and umwait

Since only the first 32 bits of input operand are used for tpause and
umwait, the REX.W bit is skipped.  Both 32-bit registers and 64-bit
registers are allowed.

gas/

	* testsuite/gas/i386/x86-64-waitpkg.s: Add 32-bit registers
	tests for tpause and umwait.
	* testsuite/gas/i386/x86-64-waitpkg-intel.d: Updated.
	* testsuite/gas/i386/x86-64-waitpkg.d: Likewise.

opcodes/

	* i386-dis.c (prefix_table): Replace Em with Edq on tpause and
	umwait.
	* i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
	64-bit mode.
	* i386-tbl.h: Regenerated.
parent 7c31c22f
2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/x86-64-waitpkg.s: Add 32-bit registers
tests for tpause and umwait.
* testsuite/gas/i386/x86-64-waitpkg-intel.d: Updated.
* testsuite/gas/i386/x86-64-waitpkg.d: Likewise.
2018-04-12 John Darrington <john@darrington.wattle.id.au>
* as.c (main): Fail if the output is the same as one of the input
......
......@@ -12,8 +12,12 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*f3 0f ae f0[ ]*umonitor rax
[ ]*[a-f0-9]+:[ ]*f3 41 0f ae f2[ ]*umonitor r10
[ ]*[a-f0-9]+:[ ]*67 f3 41 0f ae f2[ ]*umonitor r10d
[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait rcx
[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait r10
[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause rcx
[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause r10
[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait ecx
[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait ecx
[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait r10d
[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait r10d
[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause ecx
[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause ecx
[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause r10d
[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause r10d
#pass
......@@ -12,8 +12,12 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*f3 0f ae f0[ ]*umonitor %rax
[ ]*[a-f0-9]+:[ ]*f3 41 0f ae f2[ ]*umonitor %r10
[ ]*[a-f0-9]+:[ ]*67 f3 41 0f ae f2[ ]*umonitor %r10d
[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait %rcx
[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait %r10
[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause %rcx
[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause %r10
[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait %ecx
[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait %ecx
[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait %r10d
[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait %r10d
[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause %ecx
[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause %ecx
[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause %r10d
[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause %r10d
#pass
......@@ -5,7 +5,11 @@ _start:
umonitor %rax
umonitor %r10
umonitor %r10d
umwait %ecx
umwait %rcx
umwait %r10
umwait %r10d
tpause %ecx
tpause %rcx
tpause %r10
tpause %r10d
2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (prefix_table): Replace Em with Edq on tpause and
umwait.
* i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
64-bit mode.
* i386-tbl.h: Regenerated.
2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
......
......@@ -4206,8 +4206,8 @@ static const struct dis386 prefix_table[][4] = {
{
{ RM_TABLE (RM_0FAE_REG_6) },
{ "umonitor", { Eva }, PREFIX_OPCODE },
{ "tpause", { Em }, PREFIX_OPCODE },
{ "umwait", { Em }, PREFIX_OPCODE },
{ "tpause", { Edq }, PREFIX_OPCODE },
{ "umwait", { Edq }, PREFIX_OPCODE },
},
/* PREFIX_0FAE_REG_7 */
......
......@@ -5904,10 +5904,8 @@ pconfig, 0, 0x0f01c5, None, 3, CpuPCONFIG, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS
umonitor, 1, 0xf30fae, 0x6, 2, CpuWAITPKG|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOp0, { Reg16|Reg32 }
umonitor, 1, 0xf30fae, 0x6, 2, CpuWAITPKG|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOp0|NoRex64, { Reg32|Reg64 }
tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }
tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64 }
umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }
umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64 }
// WAITPKG instructions end.
......@@ -93810,41 +93810,13 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 1, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 } } } },
{ "tpause", 1, 0x660fae, 0x6, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 1, 0, 0 } },
0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0 } } } },
{ "umwait", 1, 0xf20fae, 0x6, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 1, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0 } } } },
{ "umwait", 1, 0xf20fae, 0x6, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
......@@ -93852,13 +93824,13 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 1, 0, 0 } },
0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0 } } } },
{ NULL, 0, 0, 0, 0,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment