Commit d53e6b98 authored by Jan Beulich's avatar Jan Beulich Committed by Jan Beulich

x86/Intel: correct disassembly of fsub*/fdiv*

fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly
should match (a) the Intel SDM and (b) respective input fed to gas (both
of course with the exception of when we intentionally convert bogus
insns, accompanied by a warning).
parent a477a8c4
2018-03-08 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/intel-intel.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_operands): Access operands only
......
......@@ -52,6 +52,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "opcode-intel"
run_dump_test "opcode-suffix"
run_dump_test "intel"
run_dump_test "intel-intel"
run_dump_test "intel16"
run_list_test "intelbad" ""
run_dump_test "intelok"
......
This diff is collapsed.
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vmovd): Disallow Qword memory operands.
......
......@@ -13737,10 +13737,10 @@ static const struct dis386 float_reg[][8] = {
{ "fmul", { STi, ST }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ "fsub!M", { STi, ST }, 0 },
{ "fsubM", { STi, ST }, 0 },
{ "fdiv!M", { STi, ST }, 0 },
{ "fdivM", { STi, ST }, 0 },
{ "fsub{!M|r}", { STi, ST }, 0 },
{ "fsub{M|}", { STi, ST }, 0 },
{ "fdiv{!M|r}", { STi, ST }, 0 },
{ "fdiv{M|}", { STi, ST }, 0 },
},
/* dd */
{
......@@ -13759,10 +13759,10 @@ static const struct dis386 float_reg[][8] = {
{ "fmulp", { STi, ST }, 0 },
{ Bad_Opcode },
{ FGRPde_3 },
{ "fsub!Mp", { STi, ST }, 0 },
{ "fsubMp", { STi, ST }, 0 },
{ "fdiv!Mp", { STi, ST }, 0 },
{ "fdivMp", { STi, ST }, 0 },
{ "fsub{!M|r}p", { STi, ST }, 0 },
{ "fsub{M|}p", { STi, ST }, 0 },
{ "fdiv{!M|r}p", { STi, ST }, 0 },
{ "fdiv{M|}p", { STi, ST }, 0 },
},
/* df */
{
......
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