Commit f7768225 authored by Jan Beulich's avatar Jan Beulich Committed by Jan Beulich

x86: fold a few XOP templates

Also add a new test case verifying that mixed operands of SIMD insns
with a size-less memory operand in the middle are properly rejected.
parent 5d9310c4
2018-03-22 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_template): Also match 2nd and 4th
operand's register sizes.
* testsuite/gas/i386/unspec.l, testsuite/gas/i386/unspec.s: New.
* testsuite/gas/i386/i386.exp: Run new test.
2018-03-19 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
......
......@@ -5510,10 +5510,14 @@ check_reverse:
case 4:
if (!operand_type_match (overlap3, i.types[3])
|| (check_register
&& !operand_type_register_match (i.types[2],
operand_types[2],
i.types[3],
operand_types[3])))
&& (!operand_type_register_match (i.types[1],
operand_types[1],
i.types[3],
operand_types[3])
|| !operand_type_register_match (i.types[2],
operand_types[2],
i.types[3],
operand_types[3]))))
continue;
/* Fall through. */
case 3:
......
......@@ -556,6 +556,7 @@ if [expr [istarget "i*86-*-*"] || [istarget "x86_64-*-*"]] then {
run_dump_test rept
run_dump_test pr19498
run_list_test "nop-bad-1" ""
run_list_test "unspec" ""
if [is_elf_format] then {
run_list_test_stdin "list-1" "-al"
run_list_test_stdin "list-2" "-al"
......
.*: Assembler messages:
.*:3: Error: .*vblendvpd.*
.*:4: Error: .*vblendvpd.*
.*:5: Error: .*vblendvps.*
.*:6: Error: .*vblendvps.*
.*:7: Error: .*vfmaddpd.*
.*:8: Error: .*vfmaddpd.*
.*:9: Error: .*vfmaddps.*
.*:10: Error: .*vfmaddps.*
.*:11: Error: .*vgatherdpd.*
.*:12: Error: .*vgatherdpd.*
.*:13: Error: .*vgatherdps.*
.*:14: Error: .*vgatherdps.*
.*:15: Error: .*vgatherqpd.*
.*:16: Error: .*vgatherqpd.*
.*:17: Error: .*vgatherqps.*
.*:18: Error: .*vgatherqps.*
.*:19: Error: .*vpblendvb.*
.*:20: Error: .*vpblendvb.*
.*:21: Error: .*vpcmov.*
.*:22: Error: .*vpcmov.*
.*:23: Error: .*vpermil2pd.*
.*:24: Error: .*vpermil2pd.*
.*:25: Error: .*vpermil2ps.*
.*:26: Error: .*vpermil2ps.*
.*:27: Error: .*vpgatherdd.*
.*:28: Error: .*vpgatherdd.*
.*:29: Error: .*vpgatherdq.*
.*:30: Error: .*vpgatherdq.*
.*:31: Error: .*vpgatherqd.*
.*:32: Error: .*vpgatherqd.*
.*:33: Error: .*vpgatherqq.*
.*:34: Error: .*vpgatherqq.*
.*:38: Error: .*vblendvpd.*
.*:39: Error: .*vblendvpd.*
.*:40: Error: .*vblendvps.*
.*:41: Error: .*vblendvps.*
.*:42: Error: .*vfmaddpd.*
.*:43: Error: .*vfmaddpd.*
.*:44: Error: .*vfmaddps.*
.*:45: Error: .*vfmaddps.*
.*:46: Error: .*vgatherdpd.*
.*:47: Error: .*vgatherdpd.*
.*:48: Error: .*vgatherdps.*
.*:49: Error: .*vgatherdps.*
.*:50: Error: .*vgatherqpd.*
.*:51: Error: .*vgatherqpd.*
.*:52: Error: .*vgatherqps.*
.*:53: Error: .*vgatherqps.*
.*:54: Error: .*vpblendvb.*
.*:55: Error: .*vpblendvb.*
.*:56: Error: .*vpcmov.*
.*:57: Error: .*vpcmov.*
.*:58: Error: .*vpermil2pd.*
.*:59: Error: .*vpermil2pd.*
.*:60: Error: .*vpermil2ps.*
.*:61: Error: .*vpermil2ps.*
.*:62: Error: .*vpgatherdd.*
.*:63: Error: .*vpgatherdd.*
.*:64: Error: .*vpgatherdq.*
.*:65: Error: .*vpgatherdq.*
.*:66: Error: .*vpgatherqd.*
.*:67: Error: .*vpgatherqd.*
.*:68: Error: .*vpgatherqq.*
.*:69: Error: .*vpgatherqq.*
.text
unspec:
vblendvpd %xmm0, (%eax), %ymm0, %ymm0
vblendvpd %ymm0, (%eax), %xmm0, %xmm0
vblendvps %xmm0, (%eax), %ymm0, %ymm0
vblendvps %ymm0, (%eax), %xmm0, %xmm0
vfmaddpd %xmm0, (%eax), %ymm0, %ymm0
vfmaddpd %ymm0, (%eax), %xmm0, %xmm0
vfmaddps %xmm0, (%eax), %ymm0, %ymm0
vfmaddps %ymm0, (%eax), %xmm0, %xmm0
vgatherdpd %xmm0, (%eax,%xmm1), %ymm2
vgatherdpd %ymm0, (%eax,%xmm1), %xmm2
vgatherdps %xmm0, (%eax,%xmm1), %ymm2
vgatherdps %ymm0, (%eax,%ymm1), %xmm2
vgatherqpd %xmm0, (%eax,%xmm1), %ymm2
vgatherqpd %ymm0, (%eax,%ymm1), %xmm2
vgatherqps %xmm0, (%eax,%xmm1), %ymm2
vgatherqps %xmm0, (%eax,%ymm1), %ymm2
vpblendvb %xmm0, (%eax), %ymm0, %ymm0
vpblendvb %ymm0, (%eax), %xmm0, %xmm0
vpcmov %xmm0, (%eax), %ymm0, %ymm0
vpcmov %ymm0, (%eax), %xmm0, %xmm0
vpermil2pd $0, %xmm0, (%eax), %ymm0, %ymm0
vpermil2pd $0, %ymm0, (%eax), %xmm0, %xmm0
vpermil2ps $0, %xmm0, (%eax), %ymm0, %ymm0
vpermil2ps $0, %ymm0, (%eax), %xmm0, %xmm0
vpgatherdd %xmm0, (%eax,%xmm1), %ymm2
vpgatherdd %ymm0, (%eax,%ymm1), %xmm2
vpgatherdq %xmm0, (%eax,%xmm1), %ymm2
vpgatherdq %ymm0, (%eax,%xmm1), %xmm2
vpgatherqd %xmm0, (%eax,%xmm1), %ymm2
vpgatherqd %xmm0, (%eax,%ymm1), %ymm2
vpgatherqq %xmm0, (%eax,%xmm1), %ymm2
vpgatherqq %ymm0, (%eax,%ymm1), %xmm2
.intel_syntax noprefix
vblendvpd xmm0, xmm0, [eax], ymm0
vblendvpd ymm0, ymm0, [eax], xmm0
vblendvps xmm0, xmm0, [eax], ymm0
vblendvps ymm0, ymm0, [eax], xmm0
vfmaddpd xmm0, xmm0, [eax], ymm0
vfmaddpd ymm0, ymm0, [eax], xmm0
vfmaddps xmm0, xmm0, [eax], ymm0
vfmaddps ymm0, ymm0, [eax], xmm0
vgatherdpd xmm0, [eax+xmm1], ymm2
vgatherdpd ymm0, [eax+xmm1], xmm2
vgatherdps xmm0, [eax+xmm1], ymm2
vgatherdps ymm0, [eax+ymm1], xmm2
vgatherqpd xmm0, [eax+xmm1], ymm2
vgatherqpd ymm0, [eax+ymm1], xmm2
vgatherqps xmm0, [eax+xmm1], ymm2
vgatherqps xmm0, [eax+ymm1], ymm2
vpblendvb xmm0, xmm0, [eax], ymm0
vpblendvb ymm0, ymm0, [eax], xmm0
vpcmov xmm0, xmm0, [eax], ymm0
vpcmov ymm0, ymm0, [eax], xmm0
vpermil2pd xmm0, xmm0, [eax], ymm0, 0
vpermil2pd ymm0, ymm0, [eax], xmm0, 0
vpermil2ps xmm0, xmm0, [eax], ymm0, 0
vpermil2ps ymm0, ymm0, [eax], xmm0, 0
vpgatherdd xmm0, [eax+xmm1], ymm2
vpgatherdd ymm0, [eax+ymm1], xmm2
vpgatherdq xmm0, [eax+xmm1], ymm2
vpgatherdq ymm0, [eax+xmm1], xmm2
vpgatherqd xmm0, [eax+xmm1], ymm2
vpgatherqd xmm0, [eax+ymm1], ymm2
vpgatherqq xmm0, [eax+xmm1], ymm2
vpgatherqq ymm0, [eax+ymm1], xmm2
2018-03-22 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
256-bit templates. Drop redundant leftover Disp<N>.
* i386-tlb.h: Re-generate.
2018-03-14 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv_insn_types): New.
......
......@@ -2602,16 +2602,12 @@ vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|V
// We add Imm8 to Vex_Imm4. We use Imm8 to indicate that the operand
// is an immediate. We will check if its value will fit 4 bits.
vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM }
vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM }
vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vfrczsd, 2, 0x83, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
vfrczss, 2, 0x82, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Dword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { RegYMM, Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM, RegYMM }
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM, RegXMM }
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM, RegYMM, RegYMM }
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcomb, 4, 0xcc, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomd, 4, 0xce, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomq, 4, 0xcf, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
......@@ -2620,14 +2616,10 @@ vpcomud, 4, 0xee, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreS
vpcomuq, 4, 0xef, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomuw, 4, 0xed, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomw, 4, 0xcd, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM, RegYMM }
vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM, RegYMM }
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcomltb, 3, 0xcc, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomltd, 3, 0xce, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vpcomltq, 3, 0xcf, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
......
This diff is collapsed.
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment