Commit fe0bf0fd authored by Alan Modra's avatar Alan Modra

Remove h8300-coff support

include/
	* coff/h8300.h: Delete.
bfd/
	* Makefile.am: Remove h8300-coff support.
	* coffcode.h: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* reloc16.c: Likewise.
	* targets.c: Likewise.
	* coff-h8300.c: Delete.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
binutils/
	* testsuite/binutils-all/objcopy.exp: Remove h8300-coff support.
gas/
	* config/obj-coff.h: Remove h8300-coff support.
	* config/tc-h8300.c: Likewise.
	* config/tc-h8300.h: Likewise.
	* testsuite/gas/h8300/h8300.exp: Likewise.
	* testsuite/gas/h8300/branch-coff.s: Delete.
	* testsuite/gas/h8300/branchh-coff.s: Delete.
	* testsuite/gas/h8300/branchs-coff.s: Delete.
	* testsuite/gas/h8300/ffxx1-coff.d: Delete.
	* testsuite/gas/h8300/ffxx1-coff.s: Delete.
	* testsuite/gas/h8300/h8300-coff.exp: Delete.
ld/
	* Makefile.am: Remove h8300-coff support.
	* configure.tgt: Likewise.
	* testsuite/ld-h8300/h8300.exp: Likewise.
	* emulparams/h8300.sh: Delete.
	* emulparams/h8300h.sh: Delete.
	* emulparams/h8300hn.sh: Delete.
	* emulparams/h8300s.sh: Delete.
	* emulparams/h8300sn.sh: Delete.
	* emulparams/h8300sx.sh: Delete.
	* emulparams/h8300sxn.sh: Delete.
	* scripttempl/h8300.sc: Delete.
	* scripttempl/h8300h.sc: Delete.
	* scripttempl/h8300hn.sc: Delete.
	* scripttempl/h8300s.sc: Delete.
	* scripttempl/h8300sn.sc: Delete.
	* scripttempl/h8300sx.sc: Delete.
	* scripttempl/h8300sxn.sc: Delete.
	* testsuite/ld-h8300/relax-3-coff.d: Delete.
	* testsuite/ld-h8300/relax-4-coff.d: Delete.
	* testsuite/ld-h8300/relax-5-coff.d: Delete.
	* testsuite/ld-h8300/relax-6-coff.d: Delete.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
parent fdef3943
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove h8300-coff support.
* coffcode.h: Likewise.
* config.bfd: Likewise.
* configure.ac: Likewise.
* reloc16.c: Likewise.
* targets.c: Likewise.
* coff-h8300.c: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove IEEE 695 support.
......
......@@ -281,7 +281,6 @@ BFD32_BACKENDS = \
coff-arm.lo \
coff-aux.lo \
coff-go32.lo \
coff-h8300.lo \
coff-h8500.lo \
coff-i386.lo \
coff-m68k.lo \
......@@ -465,7 +464,6 @@ BFD32_BACKENDS_CFILES = \
coff-arm.c \
coff-aux.c \
coff-go32.c \
coff-h8300.c \
coff-h8500.c \
coff-i386.c \
coff-m68k.c \
......
......@@ -615,7 +615,6 @@ BFD32_BACKENDS = \
coff-arm.lo \
coff-aux.lo \
coff-go32.lo \
coff-h8300.lo \
coff-h8500.lo \
coff-i386.lo \
coff-m68k.lo \
......@@ -799,7 +798,6 @@ BFD32_BACKENDS_CFILES = \
coff-arm.c \
coff-aux.c \
coff-go32.c \
coff-h8300.c \
coff-h8500.c \
coff-i386.c \
coff-m68k.c \
......@@ -1314,7 +1312,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-aux.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-bfd.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-go32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-h8300.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-h8500.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-i386.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-m68k.Plo@am__quote@
......
This diff is collapsed.
......@@ -2285,51 +2285,6 @@ coff_set_arch_mach_hook (bfd *abfd, void * filehdr)
break;
#endif
#ifdef H8300MAGIC
case H8300MAGIC:
arch = bfd_arch_h8300;
machine = bfd_mach_h8300;
/* !! FIXME this probably isn't the right place for this. */
abfd->flags |= BFD_IS_RELAXABLE;
break;
#endif
#ifdef H8300HMAGIC
case H8300HMAGIC:
arch = bfd_arch_h8300;
machine = bfd_mach_h8300h;
/* !! FIXME this probably isn't the right place for this. */
abfd->flags |= BFD_IS_RELAXABLE;
break;
#endif
#ifdef H8300SMAGIC
case H8300SMAGIC:
arch = bfd_arch_h8300;
machine = bfd_mach_h8300s;
/* !! FIXME this probably isn't the right place for this. */
abfd->flags |= BFD_IS_RELAXABLE;
break;
#endif
#ifdef H8300HNMAGIC
case H8300HNMAGIC:
arch = bfd_arch_h8300;
machine = bfd_mach_h8300hn;
/* !! FIXME this probably isn't the right place for this. */
abfd->flags |= BFD_IS_RELAXABLE;
break;
#endif
#ifdef H8300SNMAGIC
case H8300SNMAGIC:
arch = bfd_arch_h8300;
machine = bfd_mach_h8300sn;
/* !! FIXME this probably isn't the right place for this. */
abfd->flags |= BFD_IS_RELAXABLE;
break;
#endif
#ifdef SH_ARCH_MAGIC_BIG
case SH_ARCH_MAGIC_BIG:
case SH_ARCH_MAGIC_LITTLE:
......@@ -2888,20 +2843,6 @@ coff_set_flags (bfd * abfd,
return TRUE;
#endif
#ifdef H8300MAGIC
case bfd_arch_h8300:
switch (bfd_get_mach (abfd))
{
case bfd_mach_h8300: *magicp = H8300MAGIC; return TRUE;
case bfd_mach_h8300h: *magicp = H8300HMAGIC; return TRUE;
case bfd_mach_h8300s: *magicp = H8300SMAGIC; return TRUE;
case bfd_mach_h8300hn: *magicp = H8300HNMAGIC; return TRUE;
case bfd_mach_h8300sn: *magicp = H8300SNMAGIC; return TRUE;
default: break;
}
break;
#endif
#ifdef SH_ARCH_MAGIC_BIG
case bfd_arch_sh:
#ifdef COFF_IMAGE_WITH_PE
......
......@@ -60,7 +60,6 @@ case $targ in
arm-epoc-pe* | \
arm*-*-aout | \
arm*-*-coff | \
h8300*-*-coff | \
h8500*-*-coff | \
i[3-7]86-*-sco3.2v5*coff | \
i[3-7]86-*-sysv4* | i[3-7]86-*-unixware* | \
......@@ -132,6 +131,7 @@ case $targ in
*-*-rtemscoff* | \
a29k-* | \
arm-*-oabi | \
h8300*-*-coff | \
hppa*-*-rtems* | \
i860-*-* | \
i960-*-* | \
......@@ -565,11 +565,6 @@ case "${targ}" in
targ_defvec=h8300_elf32_linux_vec
;;
h8300*-*-*)
targ_defvec=h8300_coff_vec
targ_underscore=yes
;;
h8500-*-*)
targ_defvec=h8500_coff_vec
targ_underscore=yes
......
......@@ -14392,7 +14392,6 @@ do
fr30_elf32_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;;
frv_elf32_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
frv_elf32_fdpic_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
h8300_coff_vec) tb="$tb coff-h8300.lo reloc16.lo $coffgen" ;;
h8300_elf32_vec) tb="$tb elf32-h8300.lo elf32.lo $elf" ;;
h8300_elf32_linux_vec) tb="$tb elf32-h8300.lo elf32.lo $elf" ;;
h8500_coff_vec) tb="$tb coff-h8500.lo reloc16.lo $coffgen" ;;
......
......@@ -469,7 +469,6 @@ do
fr30_elf32_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;;
frv_elf32_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
frv_elf32_fdpic_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
h8300_coff_vec) tb="$tb coff-h8300.lo reloc16.lo $coffgen" ;;
h8300_elf32_vec) tb="$tb elf32-h8300.lo elf32.lo $elf" ;;
h8300_elf32_linux_vec) tb="$tb elf32-h8300.lo elf32.lo $elf" ;;
h8500_coff_vec) tb="$tb coff-h8500.lo reloc16.lo $coffgen" ;;
......
......@@ -29,7 +29,6 @@ coff-arm.c
coff-aux.c
coff-bfd.c
coff-go32.c
coff-h8300.c
coff-h8500.c
coff-i386.c
coff-m68k.c
......
......@@ -22,8 +22,7 @@
/* Most of this hacked by Steve Chamberlain <sac@cygnus.com>. */
/* These routines are used by coff-h8300 and coff-z8k to do
relocation.
/* These routines are used by coff-z8k to do relocation.
FIXME: This code should be rewritten to support the new COFF
linker. Basically, they need to deal with COFF relocs rather than
......
......@@ -647,7 +647,6 @@ extern const bfd_target epiphany_elf32_vec;
extern const bfd_target fr30_elf32_vec;
extern const bfd_target frv_elf32_vec;
extern const bfd_target frv_elf32_fdpic_vec;
extern const bfd_target h8300_coff_vec;
extern const bfd_target h8300_elf32_vec;
extern const bfd_target h8300_elf32_linux_vec;
extern const bfd_target h8500_coff_vec;
......@@ -1057,7 +1056,6 @@ static const bfd_target * const _bfd_target_vector[] =
&frv_elf32_vec,
&frv_elf32_fdpic_vec,
&h8300_coff_vec,
&h8300_elf32_vec,
&h8300_elf32_linux_vec,
&h8500_coff_vec,
......
2018-04-16 Alan Modra <amodra@gmail.com>
* testsuite/binutils-all/objcopy.exp: Remove h8300-coff support.
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove IEEE 695 support.
......
......@@ -77,7 +77,6 @@ proc objcopy_test {testname srcfile} {
# files in the first place, and may order things a little
# differently. Those systems should use setup_xfail here.
setup_xfail "h8300-*-coff"
setup_xfail "h8500-*-rtems*" "h8500-*-coff"
setup_xfail "hppa*-*-*"
setup_xfail "m68*-*-*coff" "m68*-*-hpux*" "m68*-*-lynxos*"
......
2018-04-16 Alan Modra <amodra@gmail.com>
* config/obj-coff.h: Remove h8300-coff support.
* config/tc-h8300.c: Likewise.
* config/tc-h8300.h: Likewise.
* testsuite/gas/h8300/h8300.exp: Likewise.
* testsuite/gas/h8300/branch-coff.s: Delete.
* testsuite/gas/h8300/branchh-coff.s: Delete.
* testsuite/gas/h8300/branchs-coff.s: Delete.
* testsuite/gas/h8300/ffxx1-coff.d: Delete.
* testsuite/gas/h8300/ffxx1-coff.s: Delete.
* testsuite/gas/h8300/h8300-coff.exp: Delete.
2018-04-16 Alan Modra <amodra@gmail.com>
* app.c: Remove IEEE 695 support.
......
......@@ -85,11 +85,6 @@
#define TARGET_FORMAT "coff-z8k"
#endif
#ifdef TC_H8300
#include "coff/h8300.h"
#define TARGET_FORMAT "coff-h8300"
#endif
#ifdef TC_H8500
#include "coff/h8500.h"
#define TARGET_FORMAT "coff-h8500"
......
......@@ -28,10 +28,7 @@
#define h8_opcodes ops
#include "opcode/h8300.h"
#include "safe-ctype.h"
#ifdef OBJ_ELF
#include "elf/h8.h"
#endif
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
......@@ -212,12 +209,10 @@ const pseudo_typeS md_pseudo_table[] =
{"page", listing_eject, 0},
{"program", s_ignore, 0},
#ifdef OBJ_ELF
{"section", h8300_elf_section, 0},
{"section.s", h8300_elf_section, 0},
{"sect", h8300_elf_section, 0},
{"sect.s", h8300_elf_section, 0},
#endif
{0, 0, 0}
};
......@@ -1372,7 +1367,6 @@ do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, cons
check_operand (operand, 0xffff, t);
bytes[0] |= operand->exp.X_add_number >> 8;
bytes[1] |= operand->exp.X_add_number >> 0;
#ifdef OBJ_ELF
/* MOVA needs both relocs to relax the second operand properly. */
if (relaxmode != 0
&& (OP_KIND(this_try->opcode->how) == O_MOVAB
......@@ -1382,7 +1376,6 @@ do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, cons
idx = BFD_RELOC_16;
fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx);
}
#endif
break;
case L_24:
check_operand (operand, 0xffffff, t);
......@@ -1399,11 +1392,9 @@ do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, cons
bytes[3] |= operand->exp.X_add_number >> 0;
if (relaxmode != 0)
{
#ifdef OBJ_ELF
if ((operand->mode & MODE) == DISP && relaxmode == 1)
idx = BFD_RELOC_H8_DISP32A16;
else
#endif
idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1;
fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx);
}
......@@ -1418,12 +1409,9 @@ do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, cons
case L_32:
size = 4;
where = (operand->mode & SIZE) == L_24 ? -1 : 0;
#ifdef OBJ_ELF
if ((operand->mode & MODE) == DISP && relaxmode == 1)
idx = BFD_RELOC_H8_DISP32A16;
else
#endif
if (relaxmode == 2)
else if (relaxmode == 2)
idx = R_MOV24B1;
else if (relaxmode == 1)
idx = R_MOVL1;
......@@ -1656,17 +1644,9 @@ build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
int x_mode = x & MODE;
if (x_mode == IMM || x_mode == DISP)
{
#ifndef OBJ_ELF
/* Remove MEMRELAX flag added in h8300.h on mov with
addressing mode "register indirect with displacement". */
if (x_mode == DISP)
x &= ~MEMRELAX;
#endif
do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2,
op_at[i] & 1, operand + i, (x & MEMRELAX) != 0,
this_try);
}
do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2,
op_at[i] & 1, operand + i, (x & MEMRELAX) != 0,
this_try);
else if (x_mode == ABS)
do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2,
op_at[i] & 1, operand + i,
......@@ -1685,14 +1665,6 @@ build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
if (operand[i].exp.X_add_number & 1)
as_warn (_("branch operand has odd offset (%lx)\n"),
(unsigned long) operand->exp.X_add_number);
#ifndef OBJ_ELF
/* The COFF port has always been off by one, changing it
now would be an incompatible change, so we leave it as-is.
We don't want to do this for ELF as we want to be
compatible with the proposed ELF format from Hitachi. */
operand[i].exp.X_add_number -= 1;
#endif
if (size16)
{
operand[i].exp.X_add_number =
......@@ -1744,7 +1716,6 @@ build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
int where = 0;
bfd_reloc_code_real_type reloc_type = R_JMPL1;
#ifdef OBJ_ELF
/* To be compatible with the proposed H8 ELF format, we
want the relocation's offset to point to the first byte
that will be modified, not to the start of the instruction. */
......@@ -1756,7 +1727,6 @@ build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
}
else
where = 1;
#endif
/* This jmp may be a jump or a branch. */
......
......@@ -26,7 +26,6 @@
/* Fixup debug sections since we will never relax them. */
#define TC_LINKRELAX_FIXUP(seg) (seg->flags & SEC_ALLOC)
#ifdef OBJ_ELF
#ifndef TE_LINUX
#define TARGET_FORMAT "elf32-h8300"
#else
......@@ -35,18 +34,12 @@
#define LOCAL_LABEL_PREFIX '.'
#define LOCAL_LABEL(NAME) (NAME[0] == '.' && NAME[1] == 'L')
#define FAKE_LABEL_NAME ".L0\001"
#endif
struct fix;
struct internal_reloc;
#define WORKING_DOT_WORD
#define COFF_MAGIC ( Smode && Nmode ? 0x8304 : Hmode && Nmode ? 0x8303 : Smode ? 0x8302 : Hmode ? 0x8301 : 0x8300)
#define IGNORE_NONSTANDARD_ESCAPES
#define tc_coff_symbol_emit_hook(a) ; /* not used */
/* No shared lib support, so we don't need to ensure externally
visible symbols can be overridden. */
#define EXTERN_FORCE_RELOC 0
......@@ -55,11 +48,8 @@ struct internal_reloc;
#define DWARF2_LINE_MIN_INSN_LENGTH 2
#define DWARF2_USE_FIXED_ADVANCE_PC 0
#ifdef OBJ_ELF
/* Provide mappings from the original H8 COFF relocation names to
their corresponding BFD relocation names. This allows us to use
most of tc-h8300.c without modifications for both ELF and COFF
ports. */
their corresponding BFD relocation names. */
#define R_MOV24B1 BFD_RELOC_H8_DIR24A8
#define R_MOVL1 BFD_RELOC_H8_DIR32A16
#define R_RELLONG BFD_RELOC_32
......@@ -74,12 +64,8 @@ struct internal_reloc;
/* We do not want to adjust any relocations to make implementation of
linker relaxations easier. */
#define tc_fix_adjustable(FIX) 0
#endif
#define LISTING_HEADER "Renesas H8/300 GAS "
#ifndef OBJ_ELF
#define RELOC_32 1234
#endif
extern int Hmode;
extern int Smode;
......
.text
h8300_branches:
bsr h8300_branches
jmp h8300_branches
jmp @r0
jmp @@16:8
jsr h8300_branches
jsr @r0
jsr @@16:8
.h8300h
.text
h8300h_branches:
bsr h8300h_branches:8
bsr h8300h_branches:16
jmp h8300h_branches
jmp @er0
jmp @@16:8
jsr h8300h_branches
jsr @er0
jsr @@16:8
.h8300s
.text
h8300s_branches:
bsr h8300s_branches:8
bsr h8300s_branches:16
jmp h8300s_branches
jmp @er0
jmp @@16:8
jsr h8300s_branches
jsr @er0
jsr @@16:8
#objdump: --prefix-addresses -dr
#name: FFxx1
# Test for FFxx:8 addressing.
.*: file format .*h8300.*
Disassembly of section .text:
...
0: 16 main
0+0400 <main>.*mov.b #0x7f,r0l
0+0402 <.*>.*mov.b @0xbb:8,r0l
0+0404 <.*>.*mov.b r0l,@0xffb9:16
0+0408 <.*>.*mov.b #0x1,r0l
0+040a <loop>.*mov.b r0l,@0xffbb:16
0+040e <delay>.*mov.w #0x0,r1
0+0412 <deloop>.*adds #1,r1
0+0414 <.*>.*bne .0 \(0x416\)
415: DISP8 deloop[+]0xffffffff
0+0416 <.*>.*rotl.b r0l
0+0418 <.*>.*bra .0 \(0x41a\)
419: DISP8 loop[+]0xffffffff
...
.equ p6ddr, 0xffb9 ;0x7f for output
.equ p6dr, 0xffbb
.equ seed, 0x01
.text
.org 0
reset: .word main ;reset vector
;
.org 0x400
main: mov.b #0x7f,r0l ;port 6 ddr = 7F
mov.b @0xffbb:8,r0l ;***test***
mov.b r0l,@p6ddr:16
;
mov.b #seed,r0l ;start with 0000001
loop: mov.b r0l,@p6dr:16 ;output to port 6
delay: mov.w #0x0000,r1
deloop: adds #1,r1
bne deloop:8 ;not = 0
rotl r0l
bra loop:8
.word 0
# Copyright (C) 2012-2018 Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#
# Some H8/300 coff tests
#
proc do_h8300_cbranch {} {
set testname "cbranch.s: h8300 conditional branch tests"
set x 0
gas_start "cbranch.s" "-al"
# Check each instruction bit pattern to verify it got
# assembled correctly.
while 1 {
expect {
-re " +\[0-9\]+ 0000 4000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0002 4000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0004 4100\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0006 4100\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0008 4200\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 000a 4300\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 000c 4400\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 000e 4400\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0010 4500\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0012 4500\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0014 4600\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0016 4700\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0018 4800\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 001a 4900\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 001c 4A00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 001e 4B00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0020 4C00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0022 4D00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0024 4E00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0026 4F00\[^\n\]*\n" { set x [expr $x+1] }
timeout { perror "timeout\n; break }
eof { break }
}
}
# This was intended to do any cleanup necessary. It kinda looks like it
# isn't needed, but just in case, please keep it in for now.
gas_finish
# Did we find what we were looking for? If not, flunk it.
if [expr $x == 20] then { pass $testname } else { fail $testname }
}
proc do_h8300_branch {} {
set testname "branch.s: h8300 branch tests"
set x 0
gas_start "branch-coff.s" "-al"
# Check each instruction bit pattern to verify it got
# assembled correctly.
while 1 {
expect {
-re " +\[0-9\]+ 0000 5500\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0002 5A000000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0006 5900\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0008 5B00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 000a 5E000000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 000e 5D00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0010 5F00\[^\n\]*\n" { set x [expr $x+1] }
timeout { perror "timeout\n; break }
eof { break }
}
}
# This was intended to do any cleanup necessary. It kinda looks like it
# isn't needed, but just in case, please keep it in for now.
gas_finish
# Did we find what we were looking for? If not, flunk it.
if [expr $x == 7] then { pass $testname } else { fail $testname }
}
proc do_h8300h_cbranch {} {
set testname "cbranchh.s: h8300h conditional branch tests"
set x 0
gas_start "cbranchh.s" "-al"
# Check each instruction bit pattern to verify it got
# assembled correctly.
while 1 {
expect {
-re " +\[0-9\]+ 0000 4000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0002 4000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0004 4100\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0006 4100\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0008 4200\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 000a 4300\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 000c 4400\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 000e 4400\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0010 4500\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0012 4500\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0014 4600\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0016 4700\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0018 4800\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 001a 4900\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 001c 4A00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 001e 4B00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0020 4C00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0022 4D00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0024 4E00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0026 4F00\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0028 58000000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 002c 58000000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0030 58100000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0034 58100000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0038 58200000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 003c 58300000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0040 58400000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0044 58400000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0048 58500000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 004c 58500000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0050 58600000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0054 58700000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0058 58800000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 005c 58900000\[^\n\]*\n" { set x [expr $x+1] }
-re " +\[0-9\]+ 0060 58A00000\[^\n\]*\n" { set x [expr $x+1] }