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Tamar Christina authored
This adds the missing Em16 constraints the rest of the instructions requiring them and also adds a testcase to test all the instructions so these are checked from now on. The Em16 operand constrains the valid registers to the lower 16 registers when used with a half precision qualifier. The list has been cross checked (by hand) through the Arm ARM version Ca. opcodes/ PR binutils/23192 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, sqdmulh, sqrdmulh): Use Em16. gas/ PR binutils/23192 * testsuite/gas/aarch64/illegal-by-element.s: New. * testsuite/gas/aarch64/illegal-by-element.d: New. * testsuite/gas/aarch64/illegal-by-element.l: New. (cherry picked from commit 45a28947 ) Signed-off-by: Tamar Christina <tamar.christina@arm.com>
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