Commit 48d86a7a authored by Tamar Christina's avatar Tamar Christina

Fix AArch64 encodings for by element instructions.

Some instructions in Armv8-a place a limitation on FP16 registers that can be
used as the register from which to select an element from.

e.g. fmla restricts Rm to 4 bits when using an FP16 register.  This restriction
does not apply for all instructions, e.g. fcmla does not have this restriction
as it gets an extra bit from the M field.

Unfortunately, this restriction to S_H was added for all _Em operands before,
meaning for a large number of instructions you couldn't use the full register
file.

This fixes the issue by introducing a new operand _Em16 which applies this
restriction only when paired with S_H and leaves the _Em and the other
qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).

Also the patch updates all instructions that should be affected by this.

opcodes/

	PR binutils/23192
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
	* aarch64-opc.c (operand_general_constraint_met_p,
	aarch64_print_operand): Likewise.
	* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
	smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
	fmlal2, fmlsl2.
	(AARCH64_OPERANDS): Add Em2.

gas/

	PR binutils/23192
	* config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
	AARCH64_OPND_Em16
	* testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
	16 registers.
	* testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
	* testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
	* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
	* testsuite/gas/aarch64/sve.d: Likewise.

include/

	PR binutils/23192
	*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.

(cherry picked from commit 369c9167d47e69aad2e260cc1db17f8c894c138b)
Signed-off-by: default avatarTamar Christina <tamar.christina@arm.com>
parent 59ee9ce5
2018-06-29 Tamar Christina <tamar.christina@arm.com>
PR binutils/23192
* config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
AARCH64_OPND_Em16
* testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
16 registers.
* testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
* testsuite/gas/aarch64/sve.d: Likewise.
2018-06-27 Alan Modra <amodra@gmail.com>
* configure.ac: Specify extra_objects with leading "config/"
......
......@@ -5099,6 +5099,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
case AARCH64_OPND_Ed:
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
case AARCH64_OPND_SM3_IMM2:
operand->reglane.regno = default_value;
break;
......@@ -5574,6 +5575,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Ed:
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
case AARCH64_OPND_SM3_IMM2:
reg_type = REG_TYPE_VN;
vector_reg_index:
......
This diff is collapsed.
/* Test file for ARMv8.3 complex arithmetics instructions. */
.text
/* Three-same operands FCMLA. */
fcmla v1.2d, v2.2d, v3.2d, #0
fcmla v1.2d, v2.2d, v3.2d, #90
fcmla v1.2d, v2.2d, v3.2d, #180
fcmla v1.2d, v2.2d, v3.2d, #270
.macro three_same op, sz
.irp rot, 0, 90, 180, 270
.irp d, 1.\sz, 2.\sz, 5.\sz, 13.\sz, 27.\sz
.irp m, 2.\sz, 3.\sz, 5.\sz, 14.\sz, 31.\sz
.irp n, 3.\sz, 4.\sz, 6.\sz, 15.\sz, 30.\sz
\op v\d, v\m, v\n, #\rot
.endr
.endr
.endr
.endr
.endm
.macro three_element op, sz1, sz2, idx
.irp rot, 0, 90, 180, 270
.irp d, 1.\sz1, 2.\sz1, 5.\sz1, 13.\sz1, 27.\sz1
.irp m, 2.\sz1, 3.\sz1, 5.\sz1, 14.\sz1, 31.\sz1
.irp n, 3.\sz2, 4.\sz2, 6.\sz2, 15.\sz2, 30.\sz2
\op v\d, v\m, v\n[\idx], #\rot
.endr
.endr
.endr
.endr
.endm
fcmla v1.2s, v2.2s, v3.2s, #90
fcmla v1.4s, v2.4s, v3.4s, #90
fcmla v1.4h, v2.4h, v3.4h, #90
fcmla v1.8h, v2.8h, v3.8h, #90
.macro three_same_rot op, sz
.irp rot, 90, 270
.irp d, 1.\sz, 2.\sz, 5.\sz, 13.\sz, 27.\sz
.irp m, 2.\sz, 3.\sz, 5.\sz, 14.\sz, 31.\sz
.irp n, 3.\sz, 4.\sz, 6.\sz, 15.\sz, 30.\sz
\op v\d, v\m, v\n, #\rot
.endr
.endr
.endr
.endr
.endm
/* Three-same operands FCMLA. */
three_same fcmla, 2d
three_same fcmla, 2s
three_same fcmla, 4s
three_same fcmla, 4h
three_same fcmla, 8h
/* Indexed element FCMLA. */
fcmla v1.4s, v2.4s, v3.s[0], #0
fcmla v1.4s, v2.4s, v3.s[0], #90
fcmla v1.4s, v2.4s, v3.s[0], #180
fcmla v1.4s, v2.4s, v3.s[0], #270
fcmla v1.4s, v2.4s, v3.s[1], #90
fcmla v1.4h, v2.4h, v3.h[0], #90
fcmla v1.4h, v2.4h, v3.h[1], #90
fcmla v1.8h, v2.8h, v3.h[0], #90
fcmla v1.8h, v2.8h, v3.h[1], #90
fcmla v1.8h, v2.8h, v3.h[2], #90
fcmla v1.8h, v2.8h, v3.h[3], #90
three_element fcmla, 4s, s, 0
three_element fcmla, 4s, s, 1
/* Three-same operands FADD. */
fcadd v1.2d, v2.2d, v3.2d, #90
fcadd v1.2d, v2.2d, v3.2d, #270
three_element fcmla, 4h, h, 0
three_element fcmla, 4h, h, 1
three_element fcmla, 8h, h, 0
three_element fcmla, 8h, h, 1
three_element fcmla, 8h, h, 2
three_element fcmla, 8h, h, 3
fcadd v1.2s, v2.2s, v3.2s, #90
fcadd v1.4s, v2.4s, v3.4s, #90
fcadd v1.4h, v2.4h, v3.4h, #90
fcadd v1.8h, v2.8h, v3.8h, #90
/* Three-same operands FADD. */
three_same_rot fcadd, 2d
three_same_rot fcadd, 2s
three_same_rot fcadd, 4s
three_same_rot fcadd, 4h
three_same_rot fcadd, 8h
This diff is collapsed.
.include "advsimd-armv8_3.s"
fadd v1.2d, v2.2d, v3.2d
fadd v1.2s, v2.2s, v3.2s
fadd v1.4s, v2.4s, v3.4s
fadd v0.4h, v0.4h, v0.4h
fadd v1.4h, v2.4h, v3.4h
fadd v0.8h, v0.8h, v0.8h
fadd v1.8h, v2.8h, v3.8h
.macro three_same_no_rot op, sz
.irp d, 1.\sz, 2.\sz, 5.\sz, 13.\sz, 27.\sz
.irp m, 2.\sz, 3.\sz, 5.\sz, 14.\sz, 31.\sz
.irp n, 3.\sz, 4.\sz, 6.\sz, 15.\sz, 30.\sz
\op v\d, v\m, v\n
.endr
.endr
.endr
.endm
three_same_no_rot fadd, 2d
three_same_no_rot fadd, 2s
three_same_no_rot fadd, 4h
three_same_no_rot fadd, 8h
This diff is collapsed.
2018-06-29 Tamar Christina <tamar.christina@arm.com>
PR binutils/23192
*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
2018-06-26 Alan Modra <amodra@gmail.com>
* elf/internal.h (ELF_SECTION_IN_SEGMENT): Revert last change.
......
......@@ -178,6 +178,8 @@ enum aarch64_opnd
AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
qualifier is S_H. */
AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
......
2018-06-29 Tamar Christina <tamar.christina@arm.com>
PR binutils/23192
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
* aarch64-opc.c (operand_general_constraint_met_p,
aarch64_print_operand): Likewise.
* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
fmlal2, fmlsl2.
(AARCH64_OPERANDS): Add Em2.
2018-06-26 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
......
......@@ -614,7 +614,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 27:
case 28:
case 29:
case 152:
case 153:
case 154:
case 155:
......@@ -624,7 +623,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 159:
case 160:
case 161:
case 174:
case 162:
case 175:
case 176:
case 177:
......@@ -633,8 +632,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 180:
case 181:
case 182:
case 186:
case 189:
case 183:
case 187:
case 190:
return aarch64_ins_regno (self, info, code, inst, errors);
case 13:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
......@@ -645,21 +645,21 @@ aarch64_insert_operand (const aarch64_operand *self,
case 30:
case 31:
case 32:
case 191:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 33:
return aarch64_ins_reglist (self, info, code, inst, errors);
case 192:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 34:
return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
return aarch64_ins_reglist (self, info, code, inst, errors);
case 35:
return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
case 36:
return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
case 37:
return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
case 38:
case 39:
case 40:
case 50:
case 41:
case 51:
case 52:
case 53:
......@@ -673,13 +673,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 61:
case 62:
case 63:
case 75:
case 64:
case 76:
case 77:
case 78:
case 149:
case 151:
case 166:
case 79:
case 150:
case 152:
case 167:
case 168:
case 169:
......@@ -687,86 +687,86 @@ aarch64_insert_operand (const aarch64_operand *self,
case 171:
case 172:
case 173:
case 174:
return aarch64_ins_imm (self, info, code, inst, errors);
case 41:
case 42:
return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
case 43:
return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
case 44:
case 45:
case 46:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 49:
case 140:
case 50:
case 141:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 64:
case 147:
return aarch64_ins_limm (self, info, code, inst, errors);
case 65:
return aarch64_ins_aimm (self, info, code, inst, errors);
case 148:
return aarch64_ins_limm (self, info, code, inst, errors);
case 66:
return aarch64_ins_imm_half (self, info, code, inst, errors);
return aarch64_ins_aimm (self, info, code, inst, errors);
case 67:
return aarch64_ins_imm_half (self, info, code, inst, errors);
case 68:
return aarch64_ins_fbits (self, info, code, inst, errors);
case 69:
case 70:
case 145:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 71:
case 144:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 146:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 72:
case 145:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 73:
case 74:
return aarch64_ins_cond (self, info, code, inst, errors);
case 79:
case 86:
return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 80:
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
case 87:
return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 81:
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
case 82:
case 83:
return aarch64_ins_addr_simm (self, info, code, inst, errors);
case 84:
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
return aarch64_ins_addr_simm (self, info, code, inst, errors);
case 85:
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
case 86:
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
case 87:
return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 88:
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 89:
return aarch64_ins_sysreg (self, info, code, inst, errors);
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
case 90:
return aarch64_ins_pstatefield (self, info, code, inst, errors);
return aarch64_ins_sysreg (self, info, code, inst, errors);
case 91:
return aarch64_ins_pstatefield (self, info, code, inst, errors);
case 92:
case 93:
case 94:
return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 95:
return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 96:
return aarch64_ins_barrier (self, info, code, inst, errors);
case 97:
return aarch64_ins_prfop (self, info, code, inst, errors);
return aarch64_ins_barrier (self, info, code, inst, errors);
case 98:
return aarch64_ins_hint (self, info, code, inst, errors);
return aarch64_ins_prfop (self, info, code, inst, errors);
case 99:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
return aarch64_ins_hint (self, info, code, inst, errors);
case 100:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 101:
case 102:
case 103:
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 104:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 105:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 106:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 107:
case 108:
case 109:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 110:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 111:
case 112:
case 113:
......@@ -779,8 +779,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 120:
case 121:
case 122:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 123:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 124:
case 125:
case 126:
......@@ -788,48 +788,49 @@ aarch64_insert_operand (const aarch64_operand *self,
case 128:
case 129:
case 130:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 131:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 132:
case 133:
case 134:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 135:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 136:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 137:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 138:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 139:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
case 140:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
case 141:
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 142:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 143:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
case 144:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
case 146:
case 147:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 148:
case 149:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
case 150:
case 151:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
case 162:
case 163:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 164:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 165:
case 166:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 183:
case 184:
case 185:
case 186:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 187:
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 188:
case 190:
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 189:
case 191:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
......
......@@ -19742,7 +19742,6 @@ aarch64_extract_operand (const aarch64_operand *self,
case 27:
case 28:
case 29:
case 152:
case 153:
case 154:
case 155:
......@@ -19752,7 +19751,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 159:
case 160:
case 161:
case 174:
case 162:
case 175:
case 176:
case 177:
......@@ -19761,8 +19760,9 @@ aarch64_extract_operand (const aarch64_operand *self,
case 180:
case 181:
case 182:
case 186:
case 189:
case 183:
case 187:
case 190:
return aarch64_ext_regno (self, info, code, inst, errors);
case 8:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
......@@ -19777,21 +19777,21 @@ aarch64_extract_operand (const aarch64_operand *self,
case 30:
case 31:
case 32:
case 191:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 33:
return aarch64_ext_reglist (self, info, code, inst, errors);
case 192:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 34:
return aarch64_ext_ldst_reglist (self, info, code, inst, errors);
return aarch64_ext_reglist (self, info, code, inst, errors);
case 35:
return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors);
return aarch64_ext_ldst_reglist (self, info, code, inst, errors);
case 36:
return aarch64_ext_ldst_elemlist (self, info, code, inst, errors);
return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors);
case 37:
return aarch64_ext_ldst_elemlist (self, info, code, inst, errors);
case 38:
case 39:
case 40:
case 50:
case 41:
case 51:
case 52:
case 53:
......@@ -19805,14 +19805,14 @@ aarch64_extract_operand (const aarch64_operand *self,
case 61:
case 62:
case 63:
case 74:
case 64:
case 75:
case 76:
case 77:
case 78:
case 149:
case 151:
case 166:
case 79:
case 150:
case 152:
case 167:
case 168:
case 169:
......@@ -19820,88 +19820,88 @@ aarch64_extract_operand (const aarch64_operand *self,
case 171:
case 172:
case 173:
case 174:
return aarch64_ext_imm (self, info, code, inst, errors);
case 41:
case 42:
return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors);
case 43:
return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors);
case 44:
case 45:
return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors);
case 46:
return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors);
case 47:
return aarch64_ext_shll_imm (self, info, code, inst, errors);
case 49:
case 140:
case 50:
case 141:
return aarch64_ext_fpimm (self, info, code, inst, errors);
case 64:
case 147:
return aarch64_ext_limm (self, info, code, inst, errors);
case 65:
return aarch64_ext_aimm (self, info, code, inst, errors);
case 148:
return aarch64_ext_limm (self, info, code, inst, errors);
case 66:
return aarch64_ext_imm_half (self, info, code, inst, errors);
return aarch64_ext_aimm (self, info, code, inst, errors);
case 67:
return aarch64_ext_imm_half (self, info, code, inst, errors);
case 68:
return aarch64_ext_fbits (self, info, code, inst, errors);
case 69:
case 70:
case 145:
return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
case 71:
case 144:
return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
case 146:
return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
case 72:
case 145:
return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
case 73:
case 74:
return aarch64_ext_cond (self, info, code, inst, errors);
case 79:
case 86:
return aarch64_ext_addr_simple (self, info, code, inst, errors);
case 80:
return aarch64_ext_addr_regoff (self, info, code, inst, errors);
case 87:
return aarch64_ext_addr_simple (self, info, code, inst, errors);
case 81:
return aarch64_ext_addr_regoff (self, info, code, inst, errors);
case 82:
case 83:
return aarch64_ext_addr_simm (self, info, code, inst, errors);
case 84:
return aarch64_ext_addr_simm10 (self, info, code, inst, errors);
return aarch64_ext_addr_simm (self, info, code, inst, errors);
case 85:
return aarch64_ext_addr_simm10 (self, info, code, inst, errors);
case 86:
return aarch64_ext_addr_uimm12 (self, info, code, inst, errors);
case 87:
return aarch64_ext_addr_offset (self, info, code, inst, errors);
case 88:
return aarch64_ext_simd_addr_post (self, info, code, inst, errors);
return aarch64_ext_addr_offset (self, info, code, inst, errors);
case 89:
return aarch64_ext_sysreg (self, info, code, inst, errors);
return aarch64_ext_simd_addr_post (self, info, code, inst, errors);
case 90:
return aarch64_ext_pstatefield (self, info, code, inst, errors);
return aarch64_ext_sysreg (self, info, code, inst, errors);
case 91:
return aarch64_ext_pstatefield (self, info, code, inst, errors);
case 92:
case 93:
case 94:
return aarch64_ext_sysins_op (self, info, code, inst, errors);
case 95:
return aarch64_ext_sysins_op (self, info, code, inst, errors);
case 96:
return aarch64_ext_barrier (self, info, code, inst, errors);
case 97:
return aarch64_ext_prfop (self, info, code, inst, errors);
return aarch64_ext_barrier (self, info, code, inst, errors);
case 98:
return aarch64_ext_hint (self, info, code, inst, errors);
return aarch64_ext_prfop (self, info, code, inst, errors);
case 99:
return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
return aarch64_ext_hint (self, info, code, inst, errors);
case 100:
return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
case 101:
case 102:
case 103:
return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 104:
return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 105:
return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 106:
return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 107:
case 108:
case 109:
return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
case 110:
return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
case 111:
case 112:
case 113:
......@@ -19914,8 +19914,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 120:
case 121:
case 122:
return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
case 123:
return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
case 124:
case 125:
case 126:
......@@ -19923,48 +19923,49 @@ aarch64_extract_operand (const aarch64_operand *self,
case 128:
case 129:
case 130:
return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
case 131:
return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
case 132:
case 133:
case 134:
return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
case 135:
return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
case 136:
return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
case 137:
return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 138:
return aarch64_ext_sve_aimm (self, info, code, inst, errors);
return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 139:
return aarch64_ext_sve_aimm (self, info, code, inst, errors);
case 140:
return aarch64_ext_sve_asimm (self, info, code, inst, errors);
case 141:
return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
case 142:
return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
case 143:
return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
case 144:
return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
case 146:
case 147:
return aarch64_ext_inv_limm (self, info, code, inst, errors);
case 148:
case 149:
return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
case 150:
case 151:
return aarch64_ext_sve_scale (self, info, code, inst, errors);
case 162:
case 163:
return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 164:
return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 165:
case 166:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
case 183:
case 184:
case 185:
case 186:
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
case 187:
return aarch64_ext_sve_index (self, info, code, inst, errors);
case 188:
case 190:
return aarch64_ext_sve_index (self, info, code, inst, errors);
case 189:
case 191:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
......@@ -372,10 +372,18 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
switch (info->qualifier)
{
case AARCH64_OPND_QLF_S_H: