Commit ec468ac4 authored by Sudakshina Das's avatar Sudakshina Das Committed by Nick Clifton

Add support for the ARM speculation barrier instructions SSBB and PSSBB.

opcodes * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
     csdb together with them.
     (thumb32_opcodes): Likewise.

gas  * config/tc-arm.c (insns): Add new ssbb and pssbb instructions.
     * testsuite/gas/arm/csdb.s: Add new tests for ssbb and pssbb.
     * testsuite/gas/arm/csdb.d: Likewise
     * testsuite/gas/arm/thumb2_it_bad.s: Likewise.
     * testsuite/gas/arm/thumb2_it_bad.l: Likewise.
     * testsuite/gas/arm/barrier.d: Update with ssbb.
     * testsuite/gas/arm/barrier-thumb.d: Likewise.
parent e87681ac
2018-07-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (insns): Add new ssbb and pssbb instructions.
* testsuite/gas/arm/csdb.s: Add new tests for ssbb and pssbb.
* testsuite/gas/arm/csdb.d: Likewise
* testsuite/gas/arm/thumb2_it_bad.s: Likewise.
* testsuite/gas/arm/thumb2_it_bad.l: Likewise.
* testsuite/gas/arm/barrier.d: Update with ssbb.
* testsuite/gas/arm/barrier-thumb.d: Likewise.
2018-07-06 Tamar Christina <tamar.christina@arm.com>
PR binutils/23369
......
......@@ -20051,6 +20051,8 @@ static const struct asm_opcode insns[] =
#define THUMB_VARIANT & arm_ext_v6t2
TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb),
TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb),
TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v6t2
......
......@@ -59,7 +59,7 @@ Disassembly of section .text:
000000b8 <[^>]*> f3bf 8f46 dsb (nshst|unst|#6)
000000bc <[^>]*> f3bf 8f43 dsb (osh|#3)
000000c0 <[^>]*> f3bf 8f6f isb (sy|#15)
000000c4 <[^>]*> f3bf 8f40 dsb #0
000000c4 <[^>]*> f3bf 8f40 ssbb
000000c8 <[^>]*> f3bf 8f4f dsb (sy|#15)
000000cc <[^>]*> f3bf 8f50 dmb #0
000000d0 <[^>]*> f3bf 8f5f dmb (sy|#15)
......
......@@ -58,7 +58,7 @@ Disassembly of section .text:
000000b8 <[^>]*> f57ff046 dsb (nshst|unst|#6)
000000bc <[^>]*> f57ff043 dsb (osh|#3)
000000c0 <[^>]*> f57ff06f isb (sy|#15)
000000c4 <[^>]*> f57ff040 dsb #0
000000c4 <[^>]*> f57ff040 ssbb
000000c8 <[^>]*> f57ff04f dsb (sy|#15)
000000cc <[^>]*> f57ff050 dmb #0
000000d0 <[^>]*> f57ff05f dmb (sy|#15)
......
......@@ -5,6 +5,9 @@
.*: +file format .*arm.*
Disassembly of section .text:
0+000 <[^>]*> f3af 8014 ? csdb
0+004 <[^>]*> e320f014 ? csdb
.*> f3af 8014 ? csdb
.*> f3bf 8f40 ? ssbb
.*> f3bf 8f44 ? pssbb
.*> e320f014 ? csdb
.*> f57ff040 ? ssbb
.*> f57ff044 ? pssbb
......@@ -2,5 +2,9 @@
.thumb
.syntax unified
csdb
ssbb
pssbb
.arm
csdb
ssbb
pssbb
......@@ -11,3 +11,5 @@
[^:]*:20: Error: instruction not allowed in IT block -- `setendeq le'
[^:]*:22: Error: IT falling in the range of a previous IT block -- `iteq eq'
[^:]*:25: Error: instruction not allowed in IT block -- `csdbeq'
[^:]*:26: Error: instruction not allowed in IT block -- `ssbbeq'
[^:]*:27: Error: instruction not allowed in IT block -- `pssbbeq'
......@@ -21,6 +21,8 @@ thumb2_it_bad:
it eq
iteq eq
nop
it eq
ittt eq
csdbeq
ssbbeq
pssbbeq
foo:
2018-07-11 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
csdb together with them.
(thumb32_opcodes): Likewise.
2018-07-06 Tamar Christina <tamar.christina@arm.com>
PR binutils/23242
......
......@@ -1846,6 +1846,11 @@ static const struct opcode32 arm_opcodes[] =
/* MP Extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
/* Speculation Barriers. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
/* V7 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
......@@ -1901,9 +1906,6 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
/* CSDB. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
/* ARM V6K NOP hints. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
0x0320f001, 0x0fffffff, "yield%c"},
......@@ -2799,6 +2801,11 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
/* Speculation Barriers. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
/* V7 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
......@@ -2822,9 +2829,6 @@ static const struct opcode32 thumb32_opcodes[] =
/* Security extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
/* CSDB. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
/* Instructions defined in the basic V6T2 set. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
......
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