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Commit 7ac379a7 authored by bjorn3's avatar bjorn3
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Fix thread spawning on aarch64

* Correctly align the stack
* Fix argument order of the ldp instructions
* Remove unnecessary ldr x5 instruction
parent dc9f3e20
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...@@ -97,10 +97,9 @@ core::arch::global_asm!( ...@@ -97,10 +97,9 @@ core::arch::global_asm!(
.p2align 6 .p2align 6
__relibc_internal_rlct_clone_ret: __relibc_internal_rlct_clone_ret:
# Load registers # Load registers
ldp x0, x8, [sp], #16 ldp x8, x0, [sp], #16
ldp x2, x1, [sp], #16 ldp x1, x2, [sp], #16
ldp x4, x3, [sp], #16 ldp x3, x4, [sp], #16
ldr x5, [sp], #16
# Call entry point # Call entry point
blr x8 blr x8
......
...@@ -174,6 +174,13 @@ pub(crate) unsafe fn create( ...@@ -174,6 +174,13 @@ pub(crate) unsafe fn create(
stack.write(value); stack.write(value);
}; };
if cfg!(target_arch = "aarch64") {
// Aarch64 requires the stack to be 16 byte aligned after
// the call instruction, unlike x86 which requires it to be
// aligned before the call instruction. As such push an
// extra word on the stack to align the stack to 16 bytes.
push(0);
}
push(0); push(0);
push(synchronization_mutex as usize); push(synchronization_mutex as usize);
push(ptr as usize); push(ptr as usize);
......
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