- Apr 22, 2020
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Jeremy Soller authored
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- Apr 21, 2020
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Jeremy Soller authored
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- Apr 20, 2020
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Jeremy Soller authored
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Jeremy Soller authored
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Jeremy Soller authored
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Jeremy Soller authored
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- Apr 19, 2020
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Jeremy Soller authored
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Jeremy Soller authored
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Jeremy Soller authored
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Jeremy Soller authored
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Jeremy Soller authored
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Jeremy Soller authored
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Jeremy Soller authored
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Jacob Lorentzon authored
since this would require pcid to know the _PRT (PCI routing table) to use and map the interrupt pins to the correct IRQs. xhcid is unaffected by this though, since it uses MSI-X. All ACPI handling will be done in userspace before the infrastructure necessary would make sense (I don't think adding serde to the kernel would be optimal, and how else would all of the ACPI namespace be parsed?).
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Jacob Lorentzon authored
and fix a typo that prevented multiple tables from being listed correctly.
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Jacob Lorentzon authored
which tells the firmware that the I/O APIC is used rather than the 8259 PIC.
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Jacob Lorentzon authored
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Jacob Lorentzon authored
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Jacob Lorentzon authored
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- Apr 18, 2020
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Jacob Lorentzon authored
which tells the firmware that the I/O APIC is used rather than the 8259 PIC.
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Jacob Lorentzon authored
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Jacob Lorentzon authored
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Jacob Lorentzon authored
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Jacob Lorentzon authored
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Jacob Lorentzon authored
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- Apr 11, 2020
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Jacob Lorentzon authored
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- Apr 04, 2020
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Jacob Lorentzon authored
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- Mar 28, 2020
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Jacob Lorentzon authored
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Jacob Lorentzon authored
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Jacob Lorentzon authored
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Jacob Lorentzon authored
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Jacob Lorentzon authored
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Jacob Lorentzon authored
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Jacob Lorentzon authored
I haven't been able to receive xhc interrupt anyway.
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- Mar 06, 2020
- Feb 19, 2020
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Jeremy Soller authored
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- Feb 13, 2020
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Jeremy Soller authored
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- Feb 11, 2020
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Jeremy Soller authored
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