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Created with Raphaël 2.2.016Mar15141311105428Feb251613109127Jan25241817817Dec161514131211715Nov9819Oct1483130Sep1816141210987643112Aug98732128Jul272625241817151410765427Jun26181312108765230May2764230Apr9114Mar129328Feb2724151130Jan1221Dec1918Nov1615141116Sep8731Aug30292827262524232221201918171613123129Jul28272626Apr251211930Mar27241912872114Feb10754328Jan30Dec130Nov2927Oct2022Sep13Aug111096131Jul11128521Jun181712May1076Ensure only the kernel can return EINTR.Accept a single RSDP from the bootloaderRemove the deprecated bootstrap_entry field from KernelArgsAvoid unaligned access in the XsdtIterRemove doc featureForce the zero page of the kernel to be part of a segmentFix bug in the unmapping codeFix get_page_info for frames in the last memory sectionDirectly read the bootstrap entry point from the initfs headerUse PAGE_SIZE instead of hard coded constantLoad the bootstrap blob at 4096 instead of 0Compile on aarch64 as well.Fix i686 compilation.Properly free phys-contiguous grants, TLB-delayed.Delay cow() dealloc until after TLB shootdown.Optimize TLB flushing.Fix synchronization so `acid tlb` succeeds!Improve synchronization.Always check shootdown reqs when locking addrsp.Use regular non-NMI IPIs for TLB shootdown.Fix lock/guard mismatch, move r#move to wrapper.Fix more synchronization.Fix flusher, currently only with -smp 1Implement a TLB shootdown draft.Build the foundation for TLB shootdown.Refactor: wrap RwLock<AddrSpace>.Fail successfully with todo!Track which CPUs are using any given AddrSpace.Improve LogicalCpu{Id,Set}, make set atomic.FormatFix affinity alignmentDon't pass CallerCtx in file_op_genericMove set_tss_stack call to switch_toRemove some dead codeAvoid unaligned access for serial over x86 io portFix UB in the locking code of context switchingShare bootstrap_mem between all archsShare idt.rs between x86 and x86_64Unify cpuid between x86 and x86_64 and don't return an OptionShare the functions in interrupt/mod.rs between x86 and x86_64